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2020 – today
- 2024
[j4]Haoyuan Wu
, Zhuolun He, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, Bei Yu:
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 3184-3197 (2024)- [c22]Haisheng Zheng, Zhuolun He, Fangzhou Liu, Zehua Pei, Bei Yu:
LSTP: A Logic Synthesis Timing Predictor. ASPDAC 2024: 728-733 - [c21]Yuan Pu, Fangzhou Liu, Yu Zhang, Zhuolun He, Yibo Lin, Kai-Yuan Chao, Bei Yu:
Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs. DAC 2024: 116:1-116:6 - [c20]Jiaxi Jiang, Lancheng Zou, Wenqian Zhao, Zhuolun He, Tinghuan Chen, Bei Yu:
PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan Geometry. DAC 2024: 119:1-119:6 - [c19]Fangzhou Liu, Zehua Pei, Ziyang Yu, Haisheng Zheng, Zhuolun He, Tinghuan Chen, Bei Yu:
CBTune: Contextual Bandit Tuning for Logic Synthesis. DATE 2024: 1-6 - [c18]Haoyuan Wu, Haisheng Zheng, Zhuolun He, Bei Yu:
Parameter-Efficient Sparsity Crafting from Dense to Mixture-of-Experts for Instruction Tuning on General Tasks. EMNLP 2024: 737-749 - [c17]Zhuolun He, Bei Yu:
Large Language Models for EDA: Future or Mirage? ISPD 2024: 65-66 - [c16]Siting Liu, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, Martin D. F. Wong:
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs. ISPD 2024: 75-82 - [c15]Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu:
IncreMacro: Incremental Macro Placement Refinement. ISPD 2024: 169-176 - [i3]Yuan Pu, Zhuolun He, Tairu Qiu, Haoyuan Wu, Bei Yu:
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA. CoRR abs/2407.15353 (2024) - 2023
- [j3]Ziyi Wang, Zhuolun He, Chen Bai, Haoyu Yang, Bei Yu:
Efficient Arithmetic Block Identification With Graph Learning and Network-Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2591-2603 (2023) - [j2]Bizhao Shi, Jiaxi Zhang, Zhuolun He, Xuechao Wei, Sicheng Li, Guojie Luo, Hongzhong Zheng, Yuan Xie:
Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3910-3924 (2023) - [c14]Yuxuan Zhao, Qi Sun, Zhuolun He, Yang Bai, Bei Yu:
AutoGraph: Optimizing DNN Computation Graph for Parallel GPU Kernel Execution. AAAI 2023: 11354-11362 - [c13]Zhuolun He, Yihang Zuo, Jiaxi Jiang, Haisheng Zheng, Yuzhe Ma, Bei Yu:
OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration. DAC 2023: 1-6 - [c12]Wei Zhong, Zhenhua Feng, Zhuolun He, Weimin Wang, Yuzhe Ma, Bei Yu:
Efficient Design Rule Checking with GPU Acceleration. DATE 2023: 1-2 - [c11]Zhuolun He, Bei Yu:
Invited Paper: Heterogeneous Acceleration for Design Rule Checking. ICCAD 2023: 1-7 - [c10]Zehua Pei, Fangzhou Liu, Zhuolun He, Guojin Chen, Haisheng Zheng, Keren Zhu, Bei Yu:
AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search. ICCAD 2023: 1-9 - [c9]Zhuolun He, Haoyuan Wu, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, Bei Yu:
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA. MLCAD 2023: 1-6 - [i2]Zhuolun He, Haoyuan Wu, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, Bei Yu:
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA. CoRR abs/2308.10204 (2023) - 2022
- [c8]Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, Yu Huang:
Functionality matters in netlist representation learning. DAC 2022: 61-66 - [c7]Zhuolun He, Yuzhe Ma, Bei Yu:
X-Check: CPU-Accelerated Design Rule Checking via Parallel Sweepline Algorithms. ICCAD 2022: 52:1-52:9 - 2021
- [c6]Zhuolun He, Peiyu Liao, Siting Liu, Yuzhe Ma, Yibo Lin, Bei Yu:
Physical Synthesis for Advanced Neural Network Processors. ASP-DAC 2021: 833-840 - [c5]Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, Bei Yu:
Graph Learning-Based Arithmetic Block Identification. ICCAD 2021: 1-8 - 2020
- [j1]Ching-Yun Ko, Cong Chen, Zhuolun He, Yuke Zhang, Kim Batselier, Ngai Wong:
Deep Model Compression and Inference Speedup of Sum-Product Networks on Tensor Trains. IEEE Trans. Neural Networks Learn. Syst. 31(7): 2665-2671 (2020) - [c4]Zhuolun He, Yuzhe Ma, Lu Zhang, Peiyu Liao, Ngai Wong, Bei Yu, Martin D. F. Wong:
Learn to Floorplan through Acquisition of Effective Local Search Heuristics. ICCD 2020: 324-331 - [c3]Yuzhe Ma, Zhuolun He, Wei Li, Lu Zhang, Bei Yu:
Understanding Graphs in EDA: From Shallow to Deep Learning. ISPD 2020: 119-126 - [i1]Rui Lin, Ching-Yun Ko, Zhuolun He, Cong Chen, Yuan Cheng, Hao Yu, Graziano Chesi, Ngai Wong:
HOTCAKE: Higher Order Tucker Articulated Kernels for Deeper CNN Compression. CoRR abs/2002.12663 (2020)
2010 – 2019
- 2018
- [c2]Zhuolun He, Hanxian Huang, Ming Jiang, Yuanchao Bai, Guojie Luo:
FPGA-Based Real-Time Super-Resolution System for Ultra High Definition Videos. FCCM 2018: 181-188 - 2017
- [c1]Zhuolun He, Guojie Luo:
FPGA Acceleration for Computational Glass-Free Displays. FPGA 2017: 267-274
Coauthor Index
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