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2020 – today
- 2020
[c10]Yoan Decoudu, Jean Simatic, Katell Morin-Allory, Laurent Fesquet:
From High-Level Synthesis to Bundled-Data Circuits. SAMOS 2020: 200-212
2010 – 2019
- 2019
- [c9]Grégoire Gimenez
, Jean Simatic, Laurent Fesquet:
From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits. ASYNC 2019: 86-95 - [c8]Yoan Decoudu, Jean Simatic, Pauline Alexandre, Katell Morin-Allory, Laurent Fesquet:
Comparison of Synchronous and Asynchronous FIR Filter Architectures. EBCCSP 2019: 1-8 - 2017
- [c7]Jean Simatic, Abdelkarim Cherkaoui, François Bertrand, Rodrigo Possamai Bastos, Laurent Fesquet:
A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines. ASYNC 2017: 65-72 - [c6]Saeed Mian Qaisar, Jean Simatic, Laurent Fesquet:
High-level synthesis of an event-driven windowing process. EBCCSP 2017: 1-8 - [c5]François Bertrand, Abdelkarim Cherkaoui, Jean Simatic, Anthony Maure, Laurent Fesquet:
CAR: On the highway towards de-synchronization. ICECS 2017: 339-343 - [c4]Ali Skaf, Jean Simatic, Laurent Fesquet:
Seeking low-power synchronous/asynchronous systems: A FIR implementation case study. ISCAS 2017: 1-4 - [c3]Assia El-Hadbi, Abdelkarim Cherkaoui, Oussama Elissati, Jean Simatic, Laurent Fesquet:
On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept. NEWCAS 2017: 305-308 - 2016
- [c2]Jean Simatic, Rodrigo Possamai Bastos, Laurent Fesquet:
High-level synthesis for event-based systems. EBCCSP 2016: 1-7 - [c1]Jean Simatic, Abdelkarim Cherkaoui, Rodrigo Possamai Bastos, Laurent Fesquet:
New asynchronous protocols for enhancing area and throughput in bundled-data pipelines. SBCCI 2016: 1-6
Coauthor Index
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