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2020 – today
- 2024
[j105]Gino A. Chacon
, Charles Williams, Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz, Vassos Soteriou:
Coherence Attacks and Countermeasures in Interposer-based Chiplet Systems. ACM Trans. Archit. Code Optim. 21(2): 23 (2024)- [j104]Tarek Mohamed, Victor M. van Santen, Lilas Alrahis, Ozgur Sinanoglu, Hussam Amrouch:
Graph Attention Networks to Identify the Impact of Transistor Degradation on Circuit Reliability. IEEE Trans. Circuits Syst. I Regul. Pap. 71(7): 3269-3281 (2024) - [j103]Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu:
Progressive Learning With Recurrent Neural Network for Sequence Classification. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1591-1595 (2024) - [c146]Paul R. Genssler, Lilas Alrahis, Ozgur Sinanoglu, Hussam Amrouch:
HDCircuit: Brain-Inspired HyperDimensional Computing for Circuit Recognition. DATE 2024: 1-2 - [c145]Mahya Morid Ahmadi, Lilas Alrahis, Ozgur Sinanoglu, Muhammad Shafique:
Camo-DNN: Layer Camouflaging to Protect DNNs against Timing Side-Channel Attacks. IOLTS 2024: 1-7 - [c144]Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu:
Obfuscation of FSMs for Secure Outsourcing of Neural Network Inference onto FPGAs. ISCAS 2024: 1-5 - [c143]Zhengyao Gu, Diego Troy Lopez, Lilas Alrahis, Ozgur Sinanoglu:
Always be Pre-Training: Representation Learning for Network Intrusion Detection with GNNs. ISQED 2024: 1-8 - [c142]Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu:
Code-Based Cryptography for Confidential Inference on FPGAs: An End-to-End Methodology. ISQED 2024: 1-8 - [c141]Zeng Wang, Lilas Alrahis, Likhitha Mankali, Johann Knechtel, Ozgur Sinanoglu:
LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust. ISVLSI 2024: 385-390 - [c140]Rupesh Raj Karn, Ozgur Sinanoglu:
Locking Decision Tree with State Permutation Obfuscation: Software Implementation. NewCAS 2024: 353-357 - [c139]Lakshmi Likhitha Mankali, Ozgur Sinanoglu, Satwik Patnaik:
INSIGHT: Attacking Industry-Adopted Learning Resilient Logic Locking Techniques Using Explainable Graph Neural Network. USENIX Security Symposium 2024 - [i60]Jitendra Bhandari, Mohammed Thari Nabeel, Likhitha Mankali, Ozgur Sinanoglu, Ramesh Karri, Johann Knechtel:
Lightweight Masking Against Static Power Side-Channel Attacks. CoRR abs/2402.03196 (2024) - [i59]Zhengyao Gu, Diego Troy Lopez, Lilas Alrahis, Ozgur Sinanoglu:
Always be Pre-Training: Representation Learning for Network Intrusion Detection with GNNs. CoRR abs/2402.18986 (2024) - [i58]Fangzhou Wang, Qijing Wang, Lilas Alrahis, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Ozgur Sinanoglu, Tsung-Yi Ho, Evangeline F. Y. Young, Johann Knechtel:
TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans. CoRR abs/2405.05590 (2024) - [i57]Zeng Wang, Lilas Alrahis, Likhitha Mankali, Johann Knechtel, Ozgur Sinanoglu:
LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust. CoRR abs/2405.07061 (2024) - [i56]Jitendra Bhandari, Animesh Basak Chowdhury, Mohammed Nabeel, Ozgur Sinanoglu, Siddharth Garg, Ramesh Karri, Johann Knechtel:
ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search. CoRR abs/2406.19549 (2024) - [i55]Prithwish Basu Roy, Johann Knechtel, Akashdeep Saha, Saideep Sreekumar, Likhitha Mankali, Mohammed Thari Nabeel, Debdeep Mukhopadhyay, Ramesh Karri, Ozgur Sinanoglu:
NiLoPher: Breaking a Modern SAT-Hardened Logic-Locking Scheme via Power Analysis Attack. IACR Cryptol. ePrint Arch. 2024: 309 (2024) - [i54]Johann Knechtel, Mohammad Eslami, Peng Zou, Min Wei, Xingyu Tong, Binggang Qiu, Zhijie Cai, Guohao Chen, Benchao Zhu, Jiawei Li, Jun Yu, Jianli Chen, Chun-Wei Chiu, Min-Feng Hsieh, Chia-Hsiu Ou, Ting-Chi Wang, Bangqi Fu, Qijing Wang, Yang Sun, Qin Luo, Anthony W. H. Lau, Fangzhou Wang, Evangeline F. Y. Young, Shunyang Bi, Guangxin Guo, Haonan Wu, Zhengguang Tang, Hailong You, Cong Li, Ramesh Karri, Ozgur Sinanoglu, Samuel Pagliarini:
Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. IACR Cryptol. ePrint Arch. 2024: 1440 (2024) - 2023
- [j102]Lilas Alrahis, Satwik Patnaik, Muhammad Abdullah Hanif, Muhammad Shafique, Ozgur Sinanoglu:
$\tt{PoisonedGNN}$: Backdoor Attack on Graph Neural Networks-Based Hardware Security Systems. IEEE Trans. Computers 72(10): 2822-2834 (2023) - [j101]Nimisha Limaye, Ozgur Sinanoglu:
RESCUE: Resilient, Scalable, High-Corruption, Compact-Key-Set Locking Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2826-2838 (2023) - [j100]Likhitha Mankali, Satwik Patnaik, Nimisha Limaye, Johann Knechtel, Ozgur Sinanoglu:
VIGILANT: Vulnerability Detection Tool Against Fault-Injection Attacks for Locking Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3571-3584 (2023) - [j99]Swetaki Chatterjee, Nikhil Rangarajan, Satwik Patnaik, Dinesh Rajasekharan, Ozgur Sinanoglu, Yogesh Singh Chauhan:
FerroCoin: Ferroelectric Tunnel Junction-Based True Random Number Generator. IEEE Trans. Emerg. Top. Comput. 11(2): 541-547 (2023) - [j98]Likhitha Mankali, Lilas Alrahis, Satwik Patnaik, Johann Knechtel, Ozgur Sinanoglu:
Titan: Security Analysis of Large-Scale Hardware Obfuscation Using Graph Neural Networks. IEEE Trans. Inf. Forensics Secur. 18: 304-318 (2023) - [j97]Dinesh Rajasekharan, Nikhil Rangarajan, Satwik Patnaik, Ozgur Sinanoglu, Yogesh Singh Chauhan:
SCANet: Securing the Weights With Superparamagnetic-MTJ Crossbar Array Networks. IEEE Trans. Neural Networks Learn. Syst. 34(9): 5693-5707 (2023) - [c138]Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu:
Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs. ASP-DAC 2023: 83-90 - [c137]Animesh Basak Chowdhury, Lilas Alrahis, Luca Collini, Johann Knechtel, Ramesh Karri, Siddharth Garg, Ozgur Sinanoglu, Benjamin Tan:
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning. DAC 2023: 1-6 - [c136]Zeng Wang, Lilas Alrahis, Dominik Sisejkovic, Ozgur Sinanoglu:
AutoLock: Automatic Design of Logic Locking with Evolutionary Computation. DSN-S 2023: 200-202 - [c135]Luca Valente, Asif Veeran, Mattia Sinigaglia, Yvan Tortorella, Alessandro Nadalini, Nils Wistoff, Bruno Sá, Angelo Garofalo, Rafail Psiakis, M. Tolba, Ari Kulmala, Nimisha Limaye, Ozgur Sinanoglu, Sandro Pinto, Daniele Palossi, Luca Benini, Baker Mohammad, Davide Rossi:
Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs. HCS 2023: 1-12 - [c134]Mahya Morid Ahmadi, Lilas Alrahis, Ozgur Sinanoglu, Muhammad Shafique:
ShapeShifter: Protecting FPGAs from Side-Channel Attacks with Isofunctional Heterogeneous Modules. IOLTS 2023: 1-7 - [c133]Hazem Lashen, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu:
TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection. ISCAS 2023: 1-5 - [c132]Mahya Morid Ahmadi, Lilas Alrahis, Ozgur Sinanoglu, Muhammad Shafique:
FPGA-Patch: Mitigating Remote Side-Channel Attacks on FPGAs using Dynamic Patch Generation. ISLPED 2023: 1-6 - [c131]Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, Ozgur Sinanoglu, Johann Knechtel, Tsung-Yi Ho, Evangeline F. Y. Young:
Security Closure of IC Layouts Against Hardware Trojans. ISPD 2023: 229-237 - [c130]Saideep Sreekumar, Mohammed Ashraf, Mohammed Thari Nabeel, Ozgur Sinanoglu, Johann Knechtel:
X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks. ISPD 2023: 238-246 - [c129]Mohammad Eslami, Johann Knechtel, Ozgur Sinanoglu, Ramesh Karri, Samuel Pagliarini:
Benchmarking Advanced Security Closure of Physical Layouts: ISPD 2023 Contest. ISPD 2023: 256-264 - [c128]Lilas Alrahis, Likhitha Mankali, Satwik Patnaik, Abhrajit Sengupta, Johann Knechtel, Ozgur Sinanoglu:
UN-SPLIT: Attacking Split Manufacturing Using Link Prediction in Graph Neural Networks. SPACE 2023: 197-213 - [c127]Lilas Alrahis, Ozgur Sinanoglu:
Graph Neural Networks for Hardware Vulnerability Analysis - Can you Trust your GNN? VTS 2023: 1-4 - [i53]Hazem Lashen, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu:
TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection. CoRR abs/2301.11804 (2023) - [i52]Animesh Basak Chowdhury, Lilas Alrahis, Luca Collini, Johann Knechtel, Ramesh Karri, Siddharth Garg, Ozgur Sinanoglu, Benjamin Tan:
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning. CoRR abs/2303.03372 (2023) - [i51]Mahya Morid Ahmadi, Lilas Alrahis, Ozgur Sinanoglu, Muhammad Shafique:
DNN-Alias: Deep Neural Network Protection Against Side-Channel Attacks via Layer Balancing. CoRR abs/2303.06746 (2023) - [i50]Lilas Alrahis, Satwik Patnaik, Muhammad Abdullah Hanif, Muhammad Shafique, Ozgur Sinanoglu:
PoisonedGNN: Backdoor Attack on Graph Neural Networks-based Hardware Security Systems. CoRR abs/2303.14009 (2023) - [i49]Lilas Alrahis, Ozgur Sinanoglu:
Graph Neural Networks for Hardware Vulnerability Analysis - Can you Trust your GNN? CoRR abs/2303.16690 (2023) - [i48]Mahya Morid Ahmadi, Lilas Alrahis, Ozgur Sinanoglu, Muhammad Shafique:
FPGA-Patch: Mitigating Remote Side-Channel Attacks on FPGAs using Dynamic Patch Generation. CoRR abs/2304.02510 (2023) - [i47]Zeng Wang, Lilas Alrahis, Dominik Sisejkovic, Ozgur Sinanoglu:
AutoLock: Automatic Design of Logic Locking with Evolutionary Computation. CoRR abs/2305.01840 (2023) - [i46]Jitendra Bhandari, Likhitha Mankali, Mohammed Nabeel, Ozgur Sinanoglu, Ramesh Karri, Johann Knechtel:
Beware Your Standard Cells! On Their Role in Static Power Side-Channel Attacks. IACR Cryptol. ePrint Arch. 2023: 920 (2023) - 2022
- [j96]Gino A. Chacon, Charles Williams, Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz:
Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems. IEEE Comput. Archit. Lett. 21(2): 133-136 (2022) - [j95]Abhrajit Sengupta, Mohammed Nabeel, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu:
A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. Cryptogr. 6(2): 22 (2022) - [j94]Nikhil Rangarajan, Johann Knechtel, Dinesh Rajasekharan, Ozgur Sinanoglu:
SuperVAULT: Superparamagnetic Volatile Auxiliary Tamper-Proof Storage. IEEE Embed. Syst. Lett. 14(2): 103-106 (2022) - [j93]Johann Knechtel, Tarek Ashraf, Natascha Fernengel, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Ozgur Sinanoglu, Hussam Amrouch:
Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology. Integr. 85: 27-34 (2022) - [j92]Satwik Patnaik, Mohammed Ashraf, Haocheng Li, Johann Knechtel, Ozgur Sinanoglu:
Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(2): 266-280 (2022) - [j91]Lilas Alrahis, Abhrajit Sengupta, Johann Knechtel, Satwik Patnaik, Hani H. Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu:
GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2435-2448 (2022) - [j90]Julian Leonhard, Nimisha Limaye, Shadi Turk, Alhassan Sayed, Alán Rodrigo Díaz Rizo, Hassan Aboushady, Ozgur Sinanoglu, Haralampos-G. Stratigopoulos:
Digitally Assisted Mixed-Signal Circuit Security. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2449-2462 (2022) - [j89]Lilas Alrahis, Johann Knechtel, Florian Klemme, Hussam Amrouch, Ozgur Sinanoglu:
GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 3826-3837 (2022) - [j88]Nikhil Rangarajan, Johann Knechtel, Nimisha Limaye, Ozgur Sinanoglu, Hussam Amrouch:
A Novel Attack Mode on Advanced Technology Nodes Exploiting Transistor Self-Heating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4134-4144 (2022) - [j87]Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, Ozgur Sinanoglu:
OMLA: An Oracle-Less Machine Learning-Based Attack on Logic Locking. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1602-1606 (2022) - [j86]Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ramesh Karri, Ozgur Sinanoglu, Shaloo Rakheja:
Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices. IEEE Trans. Emerg. Top. Comput. 10(1): 137-156 (2022) - [j85]Shubham Rai, Satwik Patnaik, Ansh Rupani, Johann Knechtel, Ozgur Sinanoglu, Akash Kumar:
Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits. IEEE Trans. Emerg. Top. Comput. 10(2): 763-778 (2022) - [j84]Nimisha Limaye, Nikhil Rangarajan, Satwik Patnaik, Ozgur Sinanoglu, Kanad Basu:
PolyWorm: Leveraging Polymorphic Behavior to Implant Hardware Trojans. IEEE Trans. Emerg. Top. Comput. 10(3): 1443-1455 (2022) - [j83]Nimisha Limaye, Christian Wachsmann, Mohammed Nabeel, Mohammed Ashraf, Arun K. Kanuparthi, Ozgur Sinanoglu:
AntiDOTE: Protecting Debug Against Outsourced Test Entities. IEEE Trans. Emerg. Top. Comput. 10(3): 1507-1518 (2022) - [j82]Lilas Alrahis, Satwik Patnaik, Muhammad Abdullah Hanif, Hani H. Saleh, Muhammad Shafique, Ozgur Sinanoglu:
GNNUnlock+: A Systematic Methodology for Designing Graph Neural Networks-Based Oracle-Less Unlocking Schemes for Provably Secure Logic Locking. IEEE Trans. Emerg. Top. Comput. 10(3): 1575-1592 (2022) - [j81]Nimisha Limaye, Satwik Patnaik, Ozgur Sinanoglu:
Valkyrie: Vulnerability Assessment Tool and Attack for Provably-Secure Logic Locking Techniques. IEEE Trans. Inf. Forensics Secur. 17: 744-759 (2022) - [j80]Satwik Patnaik, Nimisha Limaye, Ozgur Sinanoglu:
Hide and Seek: Seeking the (Un)-Hidden Key in Provably-Secure Logic Locking Techniques. IEEE Trans. Inf. Forensics Secur. 17: 3290-3305 (2022) - [c126]Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, Ozgur Sinanoglu:
MuxLink: Circumventing Learning-Resilient MUX-Locking Using Graph Neural Network-based Link Prediction. DATE 2022: 694-699 - [c125]Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, Ozgur Sinanoglu:
Embracing Graph Neural Networks for Hardware Security. ICCAD 2022: 4:1-4:9 - [c124]Tim Bücher, Lilas Alrahis, Guilherme Paim, Sergio Bampi, Ozgur Sinanoglu, Hussam Amrouch:
AppGNN: Approximation-Aware Functional Reverse Engineering Using Graph Neural Networks. ICCAD 2022: 152:1-152:9 - [c123]Mahya Morid Ahmadi, Lilas Alrahis, Alessio Colucci, Ozgur Sinanoglu, Muhammad Shafique:
NeuroUnlock: Unlocking the Architecture of Obfuscated Deep Neural Networks. IJCNN 2022: 1-10 - [c122]Johann Knechtel, Jayanth Gopinath, Mohammed Ashraf, Jitendra Bhandari, Ozgur Sinanoglu, Ramesh Karri:
Benchmarking Security Closure of Physical Layouts: ISPD 2022 Contest. ISPD 2022: 221-228 - [c121]Nikhil Rangarajan, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Shubham Rai, Gopal Raut, Heba Abunahla, Baker Mohammad, Santosh Kumar Vishvakarma, Akash Kumar, Johann Knechtel, Ozgur Sinanoglu:
SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture. ISVLSI 2022: 308-313 - [i45]Mahya Morid Ahmadi, Lilas Alrahis, Alessio Colucci, Ozgur Sinanoglu, Muhammad Shafique:
NeuroUnlock: Unlocking the Architecture of Obfuscated Deep Neural Networks. CoRR abs/2206.00402 (2022) - [i44]Lilas Alrahis, Johann Knechtel, Florian Klemme, Hussam Amrouch, Ozgur Sinanoglu:
GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation. CoRR abs/2208.02868 (2022) - [i43]Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, Ozgur Sinanoglu:
Embracing Graph Neural Networks for Hardware Security (Invited Paper). CoRR abs/2208.08554 (2022) - [i42]Tim Bücher, Lilas Alrahis, Guilherme Paim, Sergio Bampi, Ozgur Sinanoglu, Hussam Amrouch:
AppGNN: Approximation-Aware Functional Reverse Engineering using Graph Neural Networks. CoRR abs/2208.10868 (2022) - [i41]Satwik Patnaik, Nimisha Limaye, Ozgur Sinanoglu:
Hide & Seek: Seeking the (Un)-Hidden key in Provably-Secure Logic Locking Techniques. CoRR abs/2209.01711 (2022) - [i40]Gino A. Chacon, Charles Williams, Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz:
Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems. CoRR abs/2210.00058 (2022) - [i39]Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, Ozgur Sinanoglu, Johann Knechtel, Tsung-Yi Ho, Evangeline F. Y. Young:
Security Closure of IC Layouts Against Hardware Trojans. CoRR abs/2211.07997 (2022) - [i38]Saideep Sreekumar, Mohammed Ashraf, Mohammed Nabeel, Ozgur Sinanoglu, Johann Knechtel:
X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks. CoRR abs/2211.08046 (2022) - [i37]Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu:
Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs. CoRR abs/2211.16495 (2022) - [i36]Shaza Elsharief, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu:
IsoLock: Thwarting Link-Prediction Attacks on Routing Obfuscation by Graph Isomorphism. IACR Cryptol. ePrint Arch. 2022: 1752 (2022) - 2021
- [j79]Nimisha Limaye, Emmanouil Kalligeros, Nikolaos Karousos, Irene G. Karybali, Ozgur Sinanoglu:
Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(9): 1740-1753 (2021) - [j78]Haocheng Li, Satwik Patnaik, Mohammed Ashraf, Haoyu Yang, Johann Knechtel, Bei Yu, Ozgur Sinanoglu, Evangeline F. Y. Young:
Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 1995-2008 (2021) - [j77]Abhrajit Sengupta, Nimisha Limaye, Ozgur Sinanoglu:
Breaking CAS-Lock and Its Variants by Exploiting Structural Traces. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(3): 418-440 (2021) - [j76]Ozgur Sinanoglu, Ümit Y. Ogras:
Guest Editorial: Special Issue On Emerging Technologies in Computer Design. IEEE Trans. Emerg. Top. Comput. 9(1): 5-6 (2021) - [j75]Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel:
A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects. IEEE Trans. Emerg. Top. Comput. 9(4): 1815-1834 (2021) - [j74]Lilas Alrahis, Muhammad Yasin, Nimisha Limaye, Hani H. Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu:
ScanSAT: Unlocking Static and Dynamic Scan Obfuscation. IEEE Trans. Emerg. Top. Comput. 9(4): 1867-1882 (2021) - [j73]Lilas Alrahis, Satwik Patnaik, Johann Knechtel, Hani H. Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu:
UNSAIL: Thwarting Oracle-Less Machine Learning Attacks on Logic Locking. IEEE Trans. Inf. Forensics Secur. 16: 2508-2523 (2021) - [c120]Nimisha Limaye, Animesh Basak Chowdhury, Christian Pilato, Mohammed Thari Nabeel, Ozgur Sinanoglu, Siddharth Garg, Ramesh Karri:
Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks. DAC 2021: 91-96 - [c119]Lilas Alrahis, Satwik Patnaik, Faiq Khalid, Muhammad Abdullah Hanif, Hani H. Saleh, Muhammad Shafique, Ozgur Sinanoglu:
GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking. DATE 2021: 780-785 - [c118]Nimisha Limaye, Satwik Patnaik, Ozgur Sinanoglu:
Fa-SAT: Fault-aided SAT-based Attack on Compound Logic Locking Techniques. DATE 2021: 1166-1171 - [c117]Lilas Alrahis, Satwik Patnaik, Muhammad Abdullah Hanif, Muhammad Shafique, Ozgur Sinanoglu:
UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction. ICCAD 2021: 1-9 - [c116]Johann Knechtel, Jayanth Gopinath, Jitendra Bhandari, Mohammed Ashraf, Hussam Amrouch, Shekhar Borkar, Sung Kyu Lim, Ozgur Sinanoglu, Ramesh Karri:
Security Closure of Physical Layouts ICCAD Special Session Paper. ICCAD 2021: 1-9 - [c115]Jens Lienig, Susann Rothe, Matthias Thiele, Nikhil Rangarajan, Mohammed Ashraf, Mohammed Nabeel, Hussam Amrouch, Ozgur Sinanoglu, Johann Knechtel:
Toward Security Closure in the Face of Reliability Effects ICCAD Special Session Paper. ICCAD 2021: 1-9 - [i35]Tapojyoti Mandal, Gino Chacon, Johann Knechtel, Ozgur Sinanoglu, Paul Gratz, Vassos Soteriou:
Interposer-Based Root of Trust. CoRR abs/2105.02917 (2021) - [i34]Lilas Alrahis, Satwik Patnaik, Muhammad Abdullah Hanif, Muhammad Shafique, Ozgur Sinanoglu:
UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction. CoRR abs/2111.07062 (2021) - [i33]Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, Ozgur Sinanoglu:
MuxLink: Circumventing Learning-Resilient MUX-Locking Using Graph Neural Network-based Link Prediction. CoRR abs/2112.07178 (2021) - [i32]Abhrajit Sengupta, Nimisha Limaye, Ozgur Sinanoglu:
Breaking CAS-Lock and Its Variants by Exploiting Structural Traces. IACR Cryptol. ePrint Arch. 2021: 581 (2021) - 2020
- [b1]Muhammad Yasin, Jeyavijayan Rajendran, Ozgur Sinanoglu:
Trustworthy Hardware Design: Combinational Logic Locking Techniques. Springer 2020, ISBN 978-3-030-15333-5, pp. 1-137 - [j72]Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja:
SMART: A Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory. IEEE Access 8: 76130-76142 (2020) - [j71]Johann Knechtel, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Yogesh Singh Chauhan, Jörg Henkel, Ozgur Sinanoglu, Hussam Amrouch:
Power Side-Channel Attacks in Negative Capacitance Transistor. IEEE Micro 40(6): 74-84 (2020) - [j70]Mohammed Nabeel, Mohammed Ashraf, Satwik Patnaik, Vassos Soteriou, Ozgur Sinanoglu, Johann Knechtel:
2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets. IEEE Trans. Computers 69(11): 1611-1625 (2020) - [j69]Abhrajit Sengupta, Bodhisatwa Mazumdar, Muhammad Yasin, Ozgur Sinanoglu:
Logic Locking With Provable Security Against Power Analysis Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 766-778 (2020) - [j68]Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja:
Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1591-1606 (2020) - [j67]Abhishek Chakraborty, Nithyashankari Gummidipoondi Jayasankaran, Yuntao Liu, Jeyavijayan Rajendran, Ozgur Sinanoglu, Ankur Srivastava, Yang Xie, Muhammad Yasin, Michael Zuzak:
Keynote: A Disquisition on Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 1952-1972 (2020) - [j66]Abhrajit Sengupta, Mohammed Nabeel, Nimisha Limaye, Mohammed Ashraf, Ozgur Sinanoglu:
Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4439-4452 (2020) - [j65]Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel:
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4466-4481 (2020) - [j64]Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran:
Removal Attacks on Logic Locking and Camouflaging Techniques. IEEE Trans. Emerg. Top. Comput. 8(2): 517-532 (2020) - [j63]Ozgur Sinanoglu, Ümit Y. Ogras:
Guest Editors' Introduction: Special Issue on Emerging Technologies in Computer Design. IEEE Trans. Emerg. Top. Comput. 8(4): 887-888 (2020) - [c114]Nimisha Limaye, Ozgur Sinanoglu:
DynUnlock: Unlocking Scan Chains Obfuscated using Dynamic Keys. DATE 2020: 270-273 - [c113]Farimah Farahmandi, Ozgur Sinanoglu, Ronald D. Blanton, Samuel Pagliarini:
Design Obfuscation versus Test. ETS 2020: 1-10 - [i31]Nimisha Limaye, Ozgur Sinanoglu:
DynUnlock: Unlocking Scan Chains Obfuscated using Dynamic Keys. CoRR abs/2001.06724 (2020) - [i30]Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel:
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging. CoRR abs/2003.10830 (2020) - [i29]Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md. Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks:
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. CoRR abs/2006.06806 (2020) - [i28]Johann Knechtel, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Yogesh Singh Chauhan, Jörg Henkel, Ozgur Sinanoglu, Hussam Amrouch:
Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET). CoRR abs/2007.03987 (2020) - [i27]Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu:
Attacking Split Manufacturing from a Deep Learning Perspective. CoRR abs/2007.03989 (2020) - [i26]Mohammed Nabeel, Mohammed Ashraf, Satwik Patnaik, Vassos Soteriou, Ozgur Sinanoglu, Johann Knechtel:
2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets. CoRR abs/2009.02412 (2020) - [i25]Lilas Alrahis, Satwik Patnaik, Faiq Khalid, Muhammad Abdullah Hanif, Hani H. Saleh, Muhammad Shafique, Ozgur Sinanoglu:
GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking. CoRR abs/2012.05948 (2020) - [i24]Lilas Alrahis, Satwik Patnaik, Johann Knechtel, Hani H. Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu:
UNSAIL: Thwarting Oracle-Less Machine Learning Attacks on Logic Locking. CoRR abs/2012.14938 (2020)
2010 – 2019
- 2019
- [j62]Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja:
Spin-Based Reconfigurable Logic for Power- and Area-Efficient Applications. IEEE Des. Test 36(3): 22-30 (2019) - [j61]Ozgur Sinanoglu, Omer Khan:
Guest Editors Introduction: Special Section on Emerging Technologies in Computer Design. IEEE Trans. Emerg. Top. Comput. 7(2): 242-243 (2019) - [j60]Fangfei Yang, Ming Tang, Ozgur Sinanoglu:
Stripped Functionality Logic Locking With Hamming Distance-Based Restore Unit (SFLL-hd) - Unlocked. IEEE Trans. Inf. Forensics Secur. 14(10): 2778-2786 (2019) - [c112]Lilas Alrahis, Muhammad Yasin, Hani H. Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu:
ScanSAT: unlocking obfuscated scan chains. ASP-DAC 2019: 352-357 - [c111]Johann Knechtel, Satwik Patnaik, Ozgur Sinanoglu:
Protect Your Chip Design Intellectual Property: An Overview. COINS 2019: 211-216 - [c110]Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu:
Attacking Split Manufacturing from a Deep Learning Perspective. DAC 2019: 135 - [c109]Julian Leonhard, Muhammad Yasin, Shadi Turk, Mohammed Thari Nabeel, Marie-Minerve Louërat, Roselyne Chotin-Avot, Hassan Aboushady, Ozgur Sinanoglu, Haralampos-G. D. Stratigopoulos:
MixLock: Securing Mixed-Signal Circuits via Logic Locking. DATE 2019: 84-89 - [c108]Abhrajit Sengupta, Mohammed Nabeel, Johann Knechtel, Ozgur Sinanoglu:
A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. DATE 2019: 414-419 - [c107]Nimisha Limaye, Muhammad Yasin, Ozgur Sinanoglu:
Revisiting Logic Locking for Reversible Computing. ETS 2019: 1-6 - [c106]Nimisha Limaye, Abhrajit Sengupta, Mohammed Nabeel, Ozgur Sinanoglu:
Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access. ICCAD 2019: 1-8 - [c105]Johann Knechtel, Satwik Patnaik, Ozgur Sinanoglu:
3D Integration: Another Dimension Toward Hardware Security. IOLTS 2019: 147-150 - [c104]Giovanni Di Crescenzo, Abhrajit Sengupta, Ozgur Sinanoglu, Muhammad Yasin:
Logic Locking of Boolean Circuits: Provable Hardware-Based Obfuscation from a Tamper-Proof Memory. SECITC 2019: 172-192 - [c103]Julian Leonhard, Marie-Minerve Louërat, Hassan Aboushady, Ozgur Sinanoglu, Haralampos-G. D. Stratigopoulos:
Mixed-Signal Hardware Security Using MixLock: Demonstration in an Audio Application. SMACD 2019: 185-188 - [i23]Johann Knechtel, Satwik Patnaik, Ozgur Sinanoglu:
Protect Your Chip Design Intellectual Property: An Overview. CoRR abs/1902.05333 (2019) - [i22]Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja:
SMART: Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory. CoRR abs/1902.07792 (2019) - [i21]Abhrajit Sengupta, Mohammed Thari Nabeel, Johann Knechtel, Ozgur Sinanoglu:
A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. CoRR abs/1903.02913 (2019) - [i20]Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja:
Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime. CoRR abs/1904.00421 (2019) - [i19]Mohammed Nabeel, Mohammed Ashraf, Satwik Patnaik, Vassos Soteriou, Ozgur Sinanoglu, Johann Knechtel:
An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets. CoRR abs/1906.02044 (2019) - [i18]Johann Knechtel, Satwik Patnaik, Ozgur Sinanoglu:
3D Integration: Another Dimension Toward Hardware Security. CoRR abs/1906.02499 (2019) - [i17]Nimisha Limaye, Abhrajit Sengupta, Mohammed Nabeel, Ozgur Sinanoglu:
Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access. CoRR abs/1906.07806 (2019) - [i16]Johann Knechtel, Jacek Gosciniak, Alabi Bojesomo, Satwik Patnaik, Ozgur Sinanoglu, Mahmoud Rasras:
Toward Physically Unclonable Functions from Plasmonics-Enhanced Silicon Disc Resonators. CoRR abs/1907.13229 (2019) - [i15]Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel:
A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects. CoRR abs/1908.03925 (2019) - [i14]Lilas Alrahis, Muhammad Yasin, Nimisha Limaye, Hani H. Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu:
ScanSAT: Unlocking Static and Dynamic Scan Obfuscation. CoRR abs/1909.04428 (2019) - [i13]Lilas Alrahis, Muhammad Yasin, Hani H. Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu:
ScanSAT: Unlocking Obfuscated Scan Chains. IACR Cryptol. ePrint Arch. 2019: 5 (2019) - [i12]Abhrajit Sengupta, Ozgur Sinanoglu:
CAS-Unlock: Unlocking CAS-Lock without Access to a Reverse-Engineered Netlist. IACR Cryptol. ePrint Arch. 2019: 1443 (2019) - 2018
- [c102]Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Ozgur Sinanoglu:
Concerted wire lifting: Enabling secure and cost-effective split manufacturing. ASP-DAC 2018: 251-258 - [c101]Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu:
Raise your game for split manufacturing: restoring the true functionality through BEOL. DAC 2018: 140:1-140:6 - [c100]Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja:
Advancing hardware security using polymorphic and stochastic spin-hall effect devices. DATE 2018: 97-102 - [c99]Monir Zaman, Abhrajit Sengupta, Danqing Liu, Ozgur Sinanoglu, Yiorgos Makris, Jeyavijayan (JV) Rajendran:
Towards provably-secure performance locking. DATE 2018: 1592-1597 - [c98]Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel:
Best of both worlds: integration of split manufacturing and camouflaging into a security-driven CAD flow for 3D ICs. ICCAD 2018: 8 - [c97]Abhrajit Sengupta, Mohammed Thari Nabeel, Mohammed Ashraf, Ozgur Sinanoglu:
Customized locking of IP blocks on a multi-million-gate SoC. ICCAD 2018: 59 - [c96]Muhammad Yasin, Ozgur Sinanoglu:
Towards Provably Secure Logic Locking for Hardening Hardware Security Dissertation Summary: IEEE TTTC E.J. McCluskey Doctoral Thesis Award Competition. ITC 2018: 1-10 - [c95]Abhrajit Sengupta, Mohammed Thari Nabeel, Muhammad Yasin, Ozgur Sinanoglu:
ATPG-based cost-effective, secure logic locking. VTS 2018: 1-6 - [i11]Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Ozgur Sinanoglu:
Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing. CoRR abs/1806.00787 (2018) - [i10]Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja:
Advancing Hardware Security Using Polymorphic and Stochastic Spin-Hall Effect Devices. CoRR abs/1806.00790 (2018) - [i9]Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu:
Raise Your Game for Split Manufacturing: Restoring the True Functionality Through BEOL. CoRR abs/1806.09135 (2018) - [i8]Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ramesh Karri, Ozgur Sinanoglu, Shaloo Rakheja:
Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices. CoRR abs/1811.06012 (2018) - [i7]Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel:
Best of Both Worlds: Integration of Split Manufacturing and Camouflaging into a Security-Driven CAD Flow for 3D ICs. CoRR abs/1811.06822 (2018) - 2017
- [j59]Samah Mohamed Saeed, Ozgur Sinanoglu:
A Comprehensive Design-for-Test Infrastructure in the Context of Security-Critical Applications. IEEE Des. Test 34(1): 57-64 (2017) - [j58]Johann Knechtel, Ozgur Sinanoglu, Ibrahim Abe M. Elfadel, Jens Lienig, Cliff C. N. Sze:
Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration. IPSJ Trans. Syst. LSI Des. Methodol. 10: 45-62 (2017) - [j57]Chandra K. H. Suresh, Sule Ozev, Ozgur Sinanoglu:
Adaptive Reduction of the Frequency Search Space for Multi-Vdd Digital Circuits Using Variation Sensitive Ring Oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(6): 1043-1053 (2017) - [j56]Muhammad Yasin, Temesghen Tekeste, Hani H. Saleh, Baker Mohammad, Ozgur Sinanoglu, Mohammed Ismail:
Ultra-Low Power, Secure IoT Platform for Predicting Cardiovascular Diseases. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2624-2637 (2017) - [j55]Swarup Bhunia, An Chen, Ozgur Sinanoglu, Jason M. Fung:
Guest Editors Introduction: Security of Beyond CMOS Devices: Issues and Opportunities. IEEE Trans. Emerg. Top. Comput. 5(3): 302-303 (2017) - [j54]Bodhisatwa Mazumdar, Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu:
Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers. IEEE Trans. Emerg. Top. Comput. 5(3): 317-328 (2017) - [j53]Muhammad Yasin, Ozgur Sinanoglu, Jeyavijayan Rajendran:
Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging. IEEE Trans. Inf. Forensics Secur. 12(11): 2668-2682 (2017) - [c94]Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran:
Security analysis of Anti-SAT. ASP-DAC 2017: 342-347 - [c93]Muhammad Yasin, Abhrajit Sengupta, Mohammed Thari Nabeel, Mohammed Ashraf, Jeyavijayan Rajendran, Ozgur Sinanoglu:
Provably-Secure Logic Locking: From Theory To Practice. CCS 2017: 1601-1618 - [c92]Johann Knechtel, Ozgur Sinanoglu:
On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity. DAC 2017: 12:1-12:6 - [c91]Muhammad Yasin, Abhrajit Sengupta, Benjamin Carrión Schäfer, Yiorgos Makris, Ozgur Sinanoglu, Jeyavijayan Rajendran:
What to Lock?: Functional and Parametric Locking. ACM Great Lakes Symposium on VLSI 2017: 351-356 - [c90]Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu:
TTLock: Tenacious and traceless logic locking. HOST 2017: 166 - [c89]Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu:
Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging. ICCAD 2017: 41-48 - [c88]Abhrajit Sengupta, Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Siddharth Garg, Ozgur Sinanoglu:
Rethinking split manufacturing: An information-theoretic approach with secure layout techniques. ICCAD 2017: 329-326 - [c87]Muhammad Yasin, Ozgur Sinanoglu:
Evolution of logic locking. VLSI-SoC 2017: 1-6 - [e1]Ramesh Karri, Ozgur Sinanoglu, Ahmad-Reza Sadeghi, Xun Yi:
Proceedings of the 2017 ACM on Asia Conference on Computer and Communications Security, AsiaCCS 2017, Abu Dhabi, United Arab Emirates, April 2-6, 2017. ACM 2017, ISBN 978-1-4503-4944-4 [contents] - [i6]Abhrajit Sengupta, Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Siddharth Garg, Ozgur Sinanoglu:
Rethinking Split Manufacturing: An Information-Theoretic Approach with Secure Layout Techniques. CoRR abs/1710.02026 (2017) - [i5]Johann Knechtel, Ozgur Sinanoglu:
On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity. CoRR abs/1710.02678 (2017) - [i4]Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu:
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging. CoRR abs/1711.05284 (2017) - [i3]Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran:
Removal Attacks on Logic Locking and Camouflaging Techniques. IACR Cryptol. ePrint Arch. 2017: 348 (2017) - 2016
- [j52]Sk Subidh Ali, Mohamed Ibrahim, Jeyavijayan Rajendran, Ozgur Sinanoglu, Krishnendu Chakrabarty:
Supply-Chain Security of Digital Microfluidic Biochips. Computer 49(8): 36-43 (2016) - [j51]Ozgur Sinanoglu, Ramesh Karri:
Guest Editorial Special Issue on Secure and Trustworthy Computing. ACM J. Emerg. Technol. Comput. Syst. 13(1): 1:1-1:3 (2016) - [j50]Chandra K. H. Suresh, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu:
A Comparative Security Analysis of Current and Emerging Technologies. IEEE Micro 36(5): 50-61 (2016) - [j49]Muhammad Yasin, Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu, Ramesh Karri:
On Improving the Security of Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1411-1424 (2016) - [j48]Sk Subidh Ali, Mohamed Ibrahim, Ozgur Sinanoglu, Krishnendu Chakrabarty, Ramesh Karri:
Security Assessment of Cyberphysical Digital Microfluidic Biochips. IEEE ACM Trans. Comput. Biol. Bioinform. 13(3): 445-458 (2016) - [j47]Chandra K. H. Suresh, Ozgur Sinanoglu, Sule Ozev:
Adapting to Varying Distribution of Unknown Response Bits. ACM Trans. Design Autom. Electr. Syst. 21(2): 33:1-33:22 (2016) - [j46]Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu:
A Compact Implementation of Salsa20 and Its Power Analysis Vulnerabilities. ACM Trans. Design Autom. Electr. Syst. 22(1): 11:1-11:26 (2016) - [j45]Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu, Ramesh Karri:
Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach. IEEE Trans. Very Large Scale Integr. Syst. 24(9): 2946-2959 (2016) - [c86]Sk Subidh Ali, Mohamed Ibrahim, Ozgur Sinanoglu, Krishnendu Chakrabarty, Ramesh Karri:
Microfluidic encryption of on-chip biochemical assays. BioCAS 2016: 152-155 - [c85]Muhammad Yasin, Samah Mohamed Saeed, Jeyavijayan Rajendran, Ozgur Sinanoglu:
Activation of logic encrypted chips: Pre-test or post-test? DATE 2016: 139-144 - [c84]Ozgur Sinanoglu:
Do you trust your chip? DTIS 2016: 1 - [c83]Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu:
SARLock: SAT attack resistant logic locking. HOST 2016: 236-241 - [c82]Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran:
CamoPerturb: secure IC camouflaging for minterm protection. ICCAD 2016: 29 - [c81]Chandra K. H. Suresh, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu:
Power-side-channel analysis of carbon nanotube FET based design. IOLTS 2016: 215-218 - [c80]Bodhisatwa Mazumdar, Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu:
Thwarting timing attacks on NEMS relay based designs. VTS 2016: 1-4 - [i2]Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran:
Security Analysis of Anti-SAT. IACR Cryptol. ePrint Arch. 2016: 896 (2016) - [i1]Muhammad Yasin, Ozgur Sinanoglu, Jeyavijayan Rajendran:
Testing the Trustworthiness of IC Testing: An Oracle-less Attack on IC Camouflaging. IACR Cryptol. ePrint Arch. 2016: 978 (2016) - 2015
- [j44]Naghmeh Karimi, Arun Karthik Kanuparthi, Xueyang Wang, Ozgur Sinanoglu, Ramesh Karri:
MAGIC: Malicious Aging in Circuits/Cores. ACM Trans. Archit. Code Optim. 12(1): 5:1-5:25 (2015) - [j43]Jeyavijayan Rajendran, Huan Zhang, Chi Zhang, Garrett S. Rose, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri:
Fault Analysis-Based Logic Encryption. IEEE Trans. Computers 64(2): 410-424 (2015) - [j42]Sachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu, Ramesh Karri:
Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(1): 2-15 (2015) - [j41]Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, Ramesh Karri:
Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 808-821 (2015) - [j40]Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri, Ozgur Sinanoglu:
Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 822-834 (2015) - [j39]Ramesh Karri, Farinaz Koushanfar, Ozgur Sinanoglu, Yiorgos Makris, Ken Mai, Ahmad-Reza Sadeghi, Swarup Bhunia:
Guest Editorial Special Section on Hardware Security and Trust. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(6): 873-874 (2015) - [j38]Jeyavijayan Rajendran, Aman Ali, Ozgur Sinanoglu, Ramesh Karri:
Belling the CAD: Toward Security-Centric Electronic System Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1756-1769 (2015) - [j37]Chandra K. H. Suresh, Sule Ozev, Ozgur Sinanoglu:
Adaptive Generation of Unique IDs for Digital Chips through Analog Excitation. ACM Trans. Design Autom. Electr. Syst. 20(3): 46:1-46:18 (2015) - [c79]Muhammad Yasin, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu:
Security analysis of logic encryption against the most effective side-channel attack: DPA. DFTS 2015: 97-102 - [c78]Sk Subidh Ali, Ozgur Sinanoglu:
Scan attack on Elliptic Curve Cryptosystem. DFTS 2015: 115-118 - [c77]Sk Subidh Ali, Mohamed Ibrahim, Ozgur Sinanoglu, Krishnendu Chakrabarty, Ramesh Karri:
Security implications of cyberphysical digital microfluidic biochips. ICCD 2015: 483-486 - [c76]Muhammad Yasin, Ozgur Sinanoglu:
Transforming between logic locking and IC camouflaging. IDT 2015: 1-4 - [c75]Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu:
Power analysis attacks on ARX: An application to Salsa20. IOLTS 2015: 40-43 - [c74]Jerry Backer, Sk Subidh Ali, Kurt Rosenfeld, David Hély, Ozgur Sinanoglu, Ramesh Karri:
A secure design-for-test infrastructure for lifetime security of SoCs. ISCAS 2015: 37-40 - [c73]Samah Mohamed Saeed, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu:
Timing attack on NEMS relay based design of AES. VLSI-SoC 2015: 264-269 - [c72]Sk Subidh Ali, Ozgur Sinanoglu:
TMO: A new class of attack on cipher misusing test infrastructure. VTS 2015: 1-4 - 2014
- [j36]Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri:
Regaining Trust in VLSI Design: Design-for-Trust Techniques. Proc. IEEE 102(8): 1266-1282 (2014) - [j35]Samah Mohamed Saeed, Ozgur Sinanoglu:
Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 516-521 (2014) - [c71]Sachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu:
Secure Memristor-based Main Memory. DAC 2014: 178:1-178:6 - [c70]Doohwang Chang, Sule Ozev, Ozgur Sinanoglu, Ramesh Karri:
Approximating the age of RF/analog circuits through re-characterization and statistical estimation. DATE 2014: 1-4 - [c69]Abishek Ramdas, Samah Mohamed Saeed, Ozgur Sinanoglu:
Slack removal for enhanced reliability and trust. DTIS 2014: 1-4 - [c68]Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri:
Test-mode-only scan attack using the boundary scan chain. ETS 2014: 1-6 - [c67]Sk Subidh Ali, Ozgur Sinanoglu, Samah Mohamed Saeed, Ramesh Karri:
New scan attacks against state-of-the-art countermeasures and DFT. HOST 2014: 142-147 - [c66]Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri:
Test-mode-only scan attack and countermeasure for contemporary scan architectures. ITC 2014: 1-8 - [c65]Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri:
AES design space exploration new line for scan attack resiliency. VLSI-SoC 2014: 1-6 - [c64]Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri, Ozgur Sinanoglu:
Detection, diagnosis, and repair of faults in memristor-based memories. VTS 2014: 1-6 - 2013
- [j34]Samah Mohamed Saeed, Ozgur Sinanoglu:
Expedited-compact architecture for average scan power reduction. IEEE Des. Test 30(3): 25-33 (2013) - [j33]Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu:
Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints. J. Electron. Test. 29(1): 73-86 (2013) - [j32]Ozgur Sinanoglu, Vishwani D. Agrawal:
Eliminating the Timing Penalty of Scan. J. Electron. Test. 29(1): 103-114 (2013) - [j31]Ozgur Sinanoglu:
Scan to Nonscan Conversion via Test Cube Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 289-300 (2013) - [j30]Abishek Ramdas, Ozgur Sinanoglu:
Testing Chips With Spare Identical Cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(7): 1124-1135 (2013) - [j29]Samah Mohamed Saeed, Ozgur Sinanoglu, Sobeeh Almukhaizim:
Predictive Techniques for Projecting Test Data Volume Compression. IEEE Trans. Very Large Scale Integr. Syst. 21(9): 1762-1766 (2013) - [c63]Jeyavijayan Rajendran, Michael Sam, Ozgur Sinanoglu, Ramesh Karri:
Security analysis of integrated circuit camouflaging. CCS 2013: 709-720 - [c62]Chandra K. H. Suresh, Ender Yilmaz, Sule Ozev, Ozgur Sinanoglu:
Adaptive reduction of the frequency search space for multi-vdd digital circuits. DATE 2013: 292-295 - [c61]Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri:
Is split manufacturing secure? DATE 2013: 1259-1264 - [c60]Ozgur Sinanoglu, Naghmeh Karimi, Jeyavijayan Rajendran, Ramesh Karri, Yier Jin, Ke Huang, Yiorgos Makris:
Reconciling the IC test and security dichotomy. ETS 2013: 1-6 - [c59]Sachhidh Kannan, Ramesh Karri, Ozgur Sinanoglu:
Sneak path testing and fault modeling for multilevel memristor-based memories. ICCD 2013: 215-220 - [c58]Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, Ramesh Karri:
Scan attack in presence of mode-reset countermeasure. IOLTS 2013: 230-231 - [c57]Jeyavijayan Rajendran, Huan Zhang, Ozgur Sinanoglu, Ramesh Karri:
High-level synthesis for security and trust. IOLTS 2013: 232-233 - [c56]Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri:
VLSI testing based security metric for IC camouflaging. ITC 2013: 1-4 - [c55]Ozgur Sinanoglu:
Embedded tutorial: Regaining hardware security and trust. LATW 2013: 1 - [c54]Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, Ramesh Karri:
New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure. VLSI-SoC (Selected Papers) 2013: 48-68 - [c53]Sk Subidh Ali, Ozgur Sinanoglu, Samah Mohamed Saeed, Ramesh Karri:
New scan-based attack using only the test mode. VLSI-SoC 2013: 234-239 - [c52]Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu:
Sneak-path Testing of Memristor-based Memories. VLSI Design 2013: 386-391 - 2012
- [j28]Mehmet Hakan Karaata, Ozgur Sinanoglu, Bader F. AlBdaiwi:
An Optimal Inherently Stabilizing 2-Neighborhood Crash Resilient Protocol for Secure and Reliable Routing in Hypercube Networks. Comput. J. 55(5): 578-589 (2012) - [j27]Ozgur Sinanoglu:
Fault Model Independent, Maximal Compaction of Test Responses in the Presence of Unknown Response Bits. Comput. J. 55(12): 1525-1537 (2012) - [j26]Samah Mohamed Saeed, Ozgur Sinanoglu:
Multi-modal response compaction adaptive to x-density variation. IET Comput. Digit. Tech. 6(2): 69-77 (2012) - [c51]Jeyavijayan Rajendran, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri:
Security analysis of logic obfuscation. DAC 2012: 83-89 - [c50]Jeyavijayan Rajendran, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri:
Logic encryption: A fault analysis perspective. DATE 2012: 953-958 - [c49]Abishek Ramdas, Ozgur Sinanoglu:
Toggle-masking scheme for x-filtering. ETS 2012: 1-6 - [c48]Samah Mohamed Saeed, Ozgur Sinanoglu:
DfT support for launch and capture power reduction in launch-off-capture testing. ETS 2012: 1-6 - [c47]Chandra K. H. Suresh, Ozgur Sinanoglu, Sule Ozev:
Adaptive testing of chips with varying distributions of unknown response bits. ETS 2012: 1-6 - [c46]Ender Yilmaz, Sule Ozev, Ozgur Sinanoglu, Peter C. Maxwell:
Adaptive testing: Conquering process variations. ETS 2012: 1-6 - [c45]Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu:
Engineering crossbar based emerging memory technologies. ICCD 2012: 478-479 - [c44]Ozgur Sinanoglu:
Test access mechanism for chips with spare identical cores. IOLTS 2012: 97-102 - [c43]Ozgur Sinanoglu, Vishwani D. Agrawal:
Retiming scan circuit to eliminate timing penalty. LATW 2012: 1-6 - [c42]Ozgur Sinanoglu:
Eliminating Performance Penalty of Scan. VLSI Design 2012: 346-351 - 2011
- [j25]Nader Alawadhi, Ozgur Sinanoglu, Mohammed Al-Mulla:
Enhancing encoding capacity of combinational test stimulus decompressors. Sci. China Inf. Sci. 54(8): 1618-1634 (2011) - [j24]Sobeeh Almukhaizim, Ozgur Sinanoglu:
Novel hazard-free majority voter for n-modular redundancy-based fault tolerance in asynchronous circuits. IET Comput. Digit. Tech. 5(4): 306-315 (2011) - [j23]Sobeeh Almukhaizim, Eman AlQuraishi, Ozgur Sinanoglu:
Test Power Reduction via Deterministic Alignment of Stimulus and Response Bits. J. Low Power Electron. 7(4): 573-584 (2011) - [j22]Ozgur Sinanoglu, Sobeeh Almukhaizim:
Unified 2-D X-Alignment for Improving the Observability of Response Compactors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1744-1757 (2011) - [c41]Ozgur Sinanoglu:
Rewind-Support for Peak Capture Power Reduction in Launch-Off-Shift Testing. Asian Test Symposium 2011: 78-83 - [c40]Ozgur Sinanoglu:
Toggle-Based Masking Scheme for Clustered Unknown Response Bits. ETS 2011: 105-110 - [c39]Sobeeh Almukhaizim, Eman AlQuraishi, Ozgur Sinanoglu:
Test power reduction via deterministic alignment of stimulus and response bits. LATW 2011: 1-6 - [c38]Sobeeh Almukhaizim, Ozgur Sinanoglu:
Error-resilient design of branch predictors for effective yield improvement. LATW 2011: 1-6 - [c37]Samah Mohamed Saeed, Ozgur Sinanoglu:
Expedited response compaction for scan power reduction. VTS 2011: 40-45 - [c36]Jeyavijayan Rajendran, Vinayaka Jyothi, Ozgur Sinanoglu, Ramesh Karri:
Design and analysis of ring oscillator based Design-for-Trust technique. VTS 2011: 105-110 - [c35]Nader Alawadhi, Ozgur Sinanoglu:
Revival of partial scan: Test cube analysis driven conversion of flip-flops. VTS 2011: 260-265 - 2010
- [j21]Sobeeh Almukhaizim, Shouq Alsubaihi, Ozgur Sinanoglu:
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power. J. Electron. Test. 26(4): 465-481 (2010) - [j20]Ozgur Sinanoglu, Mehmet Hakan Karaata, Bader F. AlBdaiwi:
An Inherently Stabilizing Algorithm for Node-To-Node Routing over All Shortest Node-Disjoint Paths in Hypercube Networks. IEEE Trans. Computers 59(7): 995-999 (2010) - [c34]Nader Alawadhi, Ozgur Sinanoglu, Mohammed Al-Mulla:
Pattern Encodability Enhancements for Test Stimulus Decompressors. Asian Test Symposium 2010: 173-178 - [c33]Samah Mohamed Saeed, Ozgur Sinanoglu:
XOR-Based Response Compactor Adaptive to X-Density Variation. Asian Test Symposium 2010: 212-217 - [c32]Nader Alawadhi, Ozgur Sinanoglu, Mohammed Al-Mulla:
Add-on blocks and algorithms for improving stimulus compression. ETS 2010: 245 - [c31]Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu:
Reconfigurable Concurrent Error Detection adaptive to dynamicity of power constraints. ETS 2010: 248 - [c30]Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu:
Reconfigurable low-power Concurrent Error Detection in logic circuits. IDT 2010: 91-96 - [c29]Junxia Ma, Mohammad Tehranipoor, Ozgur Sinanoglu, Sobeeh Almukhaizim:
Identification of IR-drop hot-spots in defective power distribution network using TDF ATPG. IDT 2010: 122-127 - [c28]Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu:
Reconfigurable low-power Concurrent Error Detection in logic circuits. IOLTS 2010: 206-207 - [c27]Ozgur Sinanoglu, Sobeeh Almukhaizim:
Predictive analysis for projecting test compression levels. ITC 2010: 275-284
2000 – 2009
- 2009
- [j19]Ozgur Sinanoglu, Erik Jan Marinissen, Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick:
Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. IEEE Des. Test Comput. 26(3): 25-37 (2009) - [j18]Ozgur Sinanoglu, Mohammed Al-Mulla, Mohammed Nael Taha:
Utilisation of inverse compatibility for test cost reductions. IET Comput. Digit. Tech. 3(2): 195-204 (2009) - [j17]Ozgur Sinanoglu, Mohammed Al-Mulla, Noora A. Shunaiber, Alex Orailoglu:
Scan Cell Positioning for Boosting the Compression of Fan-Out Networks. J. Comput. Sci. Technol. 24(5): 939-948 (2009) - [j16]Mohammed Al-Mulla, Ozgur Sinanoglu, Mohammed Nael Taha, Nader Alawadhi:
Align-Encode Delay Assignment in the Case of XOR-Decompressors: Impact of Parallel Computations. J. Interconnect. Networks 10(4): 261-281 (2009) - [j15]Sobeeh Almukhaizim, Ozgur Sinanoglu:
Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 298-302 (2009) - [j14]Ozgur Sinanoglu, Philip Schremmer:
Scan Chain Hold-Time Violations: Can They be Tolerated? IEEE Trans. Very Large Scale Integr. Syst. 17(6): 815-826 (2009) - [j13]Ozgur Sinanoglu, Sobeeh Almukhaizim:
X-Align: Improving the Scan Cell Observability of Response Compactors. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1392-1404 (2009) - [c26]Nader Alawadhi, Ozgur Sinanoglu:
Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus Fragments. DFT 2009: 295-303 - [c25]Ozgur Sinanoglu, Sobeeh Almukhaizim:
X-alignment techniques for improving the observability of response compactors. ITC 2009: 1-10 - 2008
- [j12]Ozgur Sinanoglu:
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations. J. Electron. Test. 24(4): 335-351 (2008) - [j11]Ozgur Sinanoglu:
Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells. J. Electron. Test. 24(5): 439-448 (2008) - [j10]Ozgur Sinanoglu:
Construction of an adaptive scan network for test time and data volume reduction. IET Comput. Digit. Tech. 2(1): 12-22 (2008) - [j9]Ozgur Sinanoglu, Tsvetomir Petrov:
Isolation Techniques for Soft Cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1453-1466 (2008) - [j8]Ozgur Sinanoglu:
Scan Architecture With Align-Encode. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2303-2316 (2008) - [c24]Ozgur Sinanoglu, Erik Jan Marinissen:
Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing. DATE 2008: 182-187 - [c23]Sobeeh Almukhaizim, Ozgur Sinanoglu:
Peak Power Reduction Through Dynamic Partitioning of Scan Chains. ITC 2008: 1-10 - [c22]Ozgur Sinanoglu:
Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors. ITC 2008: 1-10 - 2007
- [j7]Ozgur Sinanoglu:
Low Cost Scan Test by Test Correlation Utilization. J. Comput. Sci. Technol. 22(5): 681-694 (2007) - [c21]Ozgur Sinanoglu, Tsvetomir Petrov:
A non-intrusive isolation approach for soft cores. DATE 2007: 27-32 - [c20]Ozgur Sinanoglu, Philip Schremmer:
Diagnosis, modeling and tolerance of scan chain hold-time violations. DATE 2007: 516-521 - 2005
- [j6]Ozgur Sinanoglu, Alex Orailoglu:
Efficient RT-Level Fault Diagnosis. J. Comput. Sci. Technol. 20(2): 166-174 (2005) - [j5]Ozgur Sinanoglu, Alex Orailoglu:
Test power reductions through computationally efficient, decoupled scan chain modifications. IEEE Trans. Reliab. 54(2): 215-223 (2005) - 2004
- [j4]Ozgur Sinanoglu, Alex Orailoglu:
Fast and energy-frugal deterministic test through efficient compression and compaction techniques. J. Syst. Archit. 50(5): 257-266 (2004) - [c19]Ozgur Sinanoglu, Alex Orailoglu:
Efficient RT-level fault diagnosis methodology. ASP-DAC 2004: 212-217 - [c18]Ozgur Sinanoglu, Alex Orailoglu:
Scan Power Minimization through Stimulus and Response Transformations. DATE 2004: 404-409 - [c17]Ozgur Sinanoglu, Alex Orailoglu:
Pipelined test of SOC cores through test data transformations. ETS 2004: 86-91 - [c16]Baris Arslan, Ozgur Sinanoglu, Alex Orailoglu:
Extending the Applicability of Parallel-Serial Scan Designs. ICCD 2004: 200-203 - [c15]Ozgur Sinanoglu, Alex Orailoglu:
Autonomous Yet Deterministic Test of SOC Cores. ITC 2004: 1359-1368 - 2003
- [j3]Ozgur Sinanoglu, Alex Orailoglu:
Compacting Test Responses for Deeply Embedded SoC Cores. IEEE Des. Test Comput. 20(4): 22-30 (2003) - [j2]Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu:
Reducing Average and Peak Test Power Through Scan Chain Modification. J. Electron. Test. 19(4): 457-467 (2003) - [c14]Ozgur Sinanoglu, Alex Orailoglu:
Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test. Asian Test Symposium 2003: 202-209 - [c13]Ozgur Sinanoglu, Alex Orailoglu:
Hierarchical Constraint Conscious RT-level Test Generation. DSD 2003: 312-318 - [c12]Ozgur Sinanoglu, Alex Orailoglu:
Parity-based output compaction for core-based SOCs [logic testing]. ETW 2003: 15-20 - [c11]Ozgur Sinanoglu, Alex Orailoglu:
Partial Core Encryption for Performance-Efficient Test of SOCs. ICCAD 2003: 91-94 - [c10]Ozgur Sinanoglu, Alex Orailoglu:
Aggressive Test Power Reduction Through Test Stimuli Transformation. ICCD 2003: 542-547 - [c9]Ozgur Sinanoglu, Alex Orailoglu:
Modeling Scan Chain Modifications For Scan-in Test Power Minimization. ITC 2003: 602-611 - 2002
- [j1]Ozgur Sinanoglu, Alex Orailoglu:
Efficient Construction of Aliasing-Free Compaction Circuitry. IEEE Micro 22(5): 82-92 (2002) - [c8]Ozgur Sinanoglu, Alex Orailoglu:
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation. DFT 2002: 325-333 - [c7]Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu:
Dynamic test data transformations for average and peak power reductions. ETW 2002: 113-118 - [c6]Ozgur Sinanoglu, Alex Orailoglu:
A novel scan architecture for power-efficient, rapid test. ICCAD 2002: 299-303 - [c5]Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu:
Scan Power Reduction Through Test Data Transition Frequency Analysis. ITC 2002: 844-850 - [c4]Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu:
Test Power Reduction through Minimization of Scan Chain Transitions. VTS 2002: 166-172 - 2001
- [c3]Ozgur Sinanoglu, Alex Orailoglu:
Compaction Schemes with Minimum Test Application Time. Asian Test Symposium 2001: 199-204 - [c2]Ozgur Sinanoglu, Alex Orailoglu:
Space and time compaction schemes for embedded cores. ITC 2001: 521-529 - [c1]Ozgur Sinanoglu, Alex Orailoglu:
RT-level Fault Simulation Based on Symbolic Propagation. VTS 2001: 240-245
Coauthor Index
Subidh Ali
aka: Sk Subidh Ali
aka: Sk Subidh Ali
[j104] [c146] [c145] [c143] [c141] [i59] [i58] [i57] [j102] [j98] [c138] [c137] [c136] [c134] [c133] [c132] [c131] [c128] [c127] [i53] [i52] [i51] [i50] [i49] [i48] [i47] [j91] [j89] [j87] [j82] [c126] [c125] [c124] [c123] [i45] [i44] [i43] [i42] [i39] [i37] [i36] [j74] [j73] [c119] [c117] [i34] [i33] [i25] [i24] [c112] [i14] [i13]
[i60] [i56] [i55] [i54] [c137] [c129] [i52] [i46] [j86] [c122] [c120] [c116] [i29] [i8] [e1] [j51] [j49] [j48] [j45] [c86] [j44] [j43] [j42] [j41] [j40] [j39] [j38] [c77] [c74] [j36] [c70] [c68] [c67] [c66] [c65] [c64] [c63] [c61] [c60] [c59] [c58] [c57] [c56] [c54] [c53] [c52] [c51] [c50] [c45] [c36]
[j105] [j103] [c144] [c142] [c141] [i60] [i58] [i57] [i56] [i55] [i54] [j100] [j98] [c138] [c137] [c133] [c131] [c130] [c129] [c128] [i53] [i52] [i46] [j96] [j95] [j94] [j93] [j92] [j91] [j89] [j88] [j86] [j85] [c122] [c121] [i44] [i40] [i39] [i38] [i37] [i36] [j78] [j75] [j73] [c116] [c115] [i35] [j72] [j71] [j70] [j68] [j65] [i30] [i28] [i27] [i26] [i24] [j62] [c111] [c110] [c108] [c105] [i23] [i22] [i21] [i20] [i19] [i18] [i16] [i15] [c102] [c101] [c100] [c98] [i11] [i10] [i9] [i8] [i7] [j58] [c92] [c89] [c88] [i6] [i5] [i4]
Likhitha Mankali
aka: Lakshmi Likhitha Mankali
aka: Lakshmi Likhitha Mankali
[c139] [j102] [j100] [j99] [j98] [j97] [c128] [i50] [j93] [j92] [j91] [j87] [j86] [j85] [j84] [j82] [j81] [j80] [c126] [c125] [c121] [i43] [i41] [j78] [j75] [j73] [c119] [c118] [c117] [i34] [i33] [j72] [j71] [j70] [j68] [j65] [i30] [i28] [i27] [i26] [i25] [i24] [j62] [c111] [c110] [c105] [i23] [i22] [i20] [i19] [i18] [i16] [i15] [c102] [c101] [c100] [c98] [i11] [i10] [i9] [i8] [i7] [c89] [c88] [i6] [i4]
Jeyavijayan Rajendran
aka: Jeyavijayan (JV) Rajendran
aka: Jeyavijayan (JV) Rajendran
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