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ORCID24th PATMOS 2014: Palma de Mallorca, Spain
- 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS), Palma de Mallorca, Spain, September 29 - Oct. 1, 2014. IEEE 2014
- Oliver Schrape, Markus Appel, Frank Winkler, Milos Krstic
:
Low-power design methodology for CML and ECL circuits. 1-5 - Christoph Roth, Christian Benkeser, Qiuting Huang:
Power-efficient turbo-decoder design based on algorithm-specific power domain partitioning. 1-6 - Lisa J. K. Durbeck, Peter Athanas:
A global perspective on energy conservation in large data networks. 1-9 - Eduarda Monteiro, Mateus Grellert, Bruno Zatt, Sergio Bampi:
Rate-distortion and energy performance of HEVC video encoders. 1-8 - Abdoul Rjoub, Nedal Al Taradeh, Mamoun F. Al-Mistarihi:
Gate leakage current accurate models for nanoscale MOSFET transistors. 1-4 - Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta:
Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications. 1-8 - Abdoul Rjoub, Areej Ahmad:
Fast modeling technique for nano scale CMOS inverter and propagation delay estimation. 1-4 - Daniel Vidal, Mario Lúcio Côrtes:
Fast and accurate solution for power estimation and DPA countermeasure design. 1-7 - Panagiotis Chaourani, Ioannis Messaris, Nikolaos Fasarakis, Maria Ntogramatzi, Sotirios K. Goudos, Spiros Nikolaidis:
An analytical model for the CMOS inverter. 1-6 - Cristian Carmona, Bartomeu Alorda, Miquel A. Ribot:
Energy consumption savings in ZigBee-based WSN adjusting power transmission at application layer. 1-6 - Bo Wang, Yang Xu, Ralph Hasholzner, Rafael Rosales, Michael Glaß, Jürgen Teich:
End-to-end power estimation for heterogeneous cellular LTE SoCs in early design phases. 1-8 - Sebastian Hesselbarth, Tim Baumgart, Holger Blume:
Hardware-assisted power estimation for design-stage processors using FPGA emulation. 1-8 - Xin Fan, Steffen Peter, Milos Krstic:
GALS design of ECC against side-channel attacks - A comparative study. 1-6 - Santhosh Kumar Rethinagiri, Oscar Palomar, Javier Arias Moreno, Osman S. Unsal, Adrián Cristal:
VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms. 1-8 - Miquel L. Alomar, Vicent Canals, Víctor Martínez-Moll, José Luis Rosselló:
Low-cost hardware implementation of Reservoir Computers. 1-5 - Dmitriy Shorin, Armin Zimmermann:
Formal description of an approach for power consumption estimation of embedded systems. 1-10 - Felipe Rosa, Luciano Ost, Thiago Raupp da Rosa, Fernando Gehm Moraes, Ricardo Reis:
Fast energy evaluation of embedded applications for many-core systems. 1-6 - Jesús Sánchez, José Miguel Gil-García, José Antonio Sainz, Miquel Roca, Eugeni Isern:
Method to evaluate energy saving techniques in data buses. 1-7 - Manuel Llamas, Mohammad Mashayekhi, Jordi Carrabina, Jody Maick Matos, André Inácio Reis:
Optimization on cell-library design for digital Application Specific Printed Electronics Circuits. 1-6 - Akiya Baba, Nanoka Sumi, Vasily G. Moshnyaga:
Impact of computation offloading on efficiency of wireless face recognition. 1-7 - Syed Abbas Ali Shah, Jan Wagner, Thomas Schuster, Mladen Berekovic:
A lightweight-system-level power and area estimation methodology for application specific instruction set processors. 1-5 - Amir Morad, Leonid Yavits, Ran Ginosar:
Efficient Dense and Sparse Matrix Multiplication on GP-SIMD. 1-8 - Dominik Macko, Katarína Jelemenská, Pavel Cicák:
Power-efficient power-management logic. 1-7 - Adedotun Adeyemo, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Write scheme for multiple Complementary Resistive Switch (CRS) cells. 1-5 - Fabian Mischkalla, Wolfgang Müller:
Advanced SoC virtual prototyping for system-level power planning and validation. 1-8 - Jimmy Tarrillo, Fernanda Lima Kastensmidt:
Estimating power consumption of multiple modular redundant designs in SRAM-based FPGAs for high dependable applications. 1-7 - Efraim Rotem, Uri C. Weiser, Avi Mendelson, Ahmad Yasin, Ran Ginosar:
Energy management of highly dynamic server workloads in an heterogeneous data center. 1-5 - Jae Min Kim, Minyong Kim, Sung Woo Chung:
Application-aware scaling governor for wearable devices. 1-8 - Robert Najvirt, Andreas Steininger:
Equivalence of clock gating and synchronization with applicability to GALS communication. 1-8 - Nasim Pour Aryan, Nils Heidmann, Martin Wirnshofer, Nico Hellwege, Jonas Pistor, Dagmar Peters-Drolshagen, Georg Georgakos, Steffen Paul, Doris Schmitt-Landsiedel:
Power efficient digital IC design for a medical application with high reliability requirements. 1-5 - Jiaoyan Chen, Arnaud Tisserand, Emanuel M. Popovici, Sorin Cotofana:
Robust sub-powered asynchronous logic. 1-7 - Giannis Petrousov, Minas Dasygenis:
A unique network EDA tool to create optimized ad hoc binary to residue number system converters. 1-8 - Axel Reimer, Wolfgang Nebel:
A methodology for scaling power dissipation values between different FPGAs. 1-8 - Eduardo Chielle, Fernanda Lima Kastensmidt, Sergio Cuenca-Asensi:
Tuning software-based fault-tolerance techniques for power optimization. 1-7 - Yang Xu, Bo Wang, Jürgen Teich:
Parametric yield optimization using leakage-yield-driven floorplanning. 1-6 - Haider Alrudainy, Andrey Mokhov, Alex Yakovlev:
A scalable physical model for Nano-Electro-Mechanical relays. 1-7 - Sebastien Bernard, Marc Belleville, Alexandre Valentian, Jean-Didier Legat, David Bol:
Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature. 1-7 - Chris Dobson, Kurt Rooks, Peter M. Athanas:
A power-efficient FPGA-based self-adaptive software defined radio. 1-8 - Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis:
Evaluating the impact of environment and physical variability on the ION current of 20nm FinFET devices. 1-8 - Sara Vinco, Alessandro Sassone, Davide Lasorsa, Enrico Macii, Massimo Poncino:
A framework for efficient evaluation and comparison of EES Models. 1-8 - Amir Morad, Leonid Yavits, Ran Ginosar:
Convex optimization of resource allocation in asymmetric and heterogeneous SoC. 1-8 - Minas Dasygenis:
A distributed VHDL compiler and simulator accessible from the web. 1-7 - Juan Núñez, Maria J. Avedillo, Hector J. Quintero:
DOE based high-performance gate-level pipelines. 1-4
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