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ORCID7th NOCS 2013: Tempe, AZ, USA
- 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Tempe, AZ, USA, April 21-24, 2013. IEEE 2013, ISBN 978-1-4673-6491-1
- Yean-Ru Chen, Zi-Rong Wangt, Pao-Ann Hsiung, Sao-Jie Chen
, Meng-Hsun Tsai:
Backward probing deadlock detection for networks-on-chip. 1-2 - Syed Minhaj Hassan, Sudhakar Yalamanchili:
Centralized buffer router: A low latency, low power router for high radix NOCs. 1-8 - Xueqian Zhao, Zhonghai Lu:
Per-flow delay bound analysis based on a formalized microarchitectural model. 1-8 - Nithin Michael, Yao Wang, G. Edward Suh, Ao Tang:
Quadrisection-based task mapping on many-core processors for energy-efficient on-chip communication. 1-2 - Jinho Lee, Kiyoung Choi:
A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections. 1-2 - Shomit Das, Georgios Manetas, Kenneth S. Stevens, Roberto Suaya:
Leveraging the geometric properties of on-chip transmission line structures to improve interconnect performance: A case study in 65nm. 1-2 - Erik Fischer, Gerhard P. Fettweis:
An accurate and scalable analytic model for round-robin arbitration in network-on-chip. 1-8 - Javier de San Pedro, Nikita Nikitin, Jordi Cortadella, Jordi Petit:
Physical planning for the architectural exploration of large-scale chip multiprocessors. 1-2 - Ran Manevich, Israel Cidon, Avinoam Kolodny:
Dynamic traffic distribution among hierarchy levels in hierarchical Networks-on-Chip (NoCs). 1-8 - Marcus Eggenberger, Martin Radetzki:
Scalable parallel simulation of networks on chip. 1-8 - Bo Zhao, Youtao Zhang, Jun Yang:
A speculative arbiter design to enable high-frequency many-VC router in NoCs. 1-8 - Xiaohang Wang, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi:
On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. 1-8 - Erfan Azarkhish, Igor Loi, Luca Benini:
3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters. 1-2 - Sean Franey, Mikko H. Lipasti:
Accelerating atomic operations on GPGPUs. 1-8 - Amit Verma, Pritpal S. Multani, Daniel Mueller-Gritschneder, Vladimir Todorov, Ulf Schlichtmann:
A greedy approach for latency-bounded deadlock-free routing path allocation for application-specific NoCs. 1-7 - Celine Azar, Stéphane Chevobbe, Yves Lhuillier, Jean-Philippe Diguet:
SNet, a flexible, scalable network paradigm for manycore architectures. 1-2 - Mukund Ramakrishna, Paul V. Gratz, Alexander Sprintson:
GCA: Global congestion awareness for load balance in Networks-on-Chip. 1-8 - Li Zhou, Avinash Karanth Kodi:
PROBE: Prediction-based optical bandwidth scaling for energy-efficient NoCs. 1-8 - Mario Lodde, José Flich:
An NoC and cache hierarchy substrate to address effective virtualization and fault-tolerance. 1-8 - Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Hannu Tenhunen:
Minimal-path fault-tolerant approach using connection-retaining structure in Networks-on-Chip. 1-8 - Dominic DiTomaso, Avinash Karanth Kodi, David W. Matolak, Savas Kaya, Soumyasanta Laha, William Rayess:
Energy-efficient adaptive wireless NoCs architecture. 1-8 - Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture. 1-8
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