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ORCIDITC-Asia 2018: Harbin, China
- IEEE International Test Conference in Asia, ITC-Asia 2018, Harbin, China, August 15-17, 2018. IEEE 2018, ISBN 978-1-5386-5180-3
- Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy:
Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run. 1-6 - Ruifeng Guo
, Brian Archer, Kevin Chau, Xiaolei Cai:
Efficient Cell-Aware Defect Characterization for Multi-bit Cells. 7-12 - Harm van Schaaijk, Martien Spierings, Erik Jan Marinissen:
Automatic Generation of In-Circuit Tests for Board Assembly Defects. 13-18 - Jia-Yun Hu, Kuan-Wei Hou, Chih-Yen Lo, Yung-Fa Chou, Cheng-Wen Wu:
RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction. 19-24 - Desong Pang, Dawen Xu, Ying Wang, Huaguo Liang:
MTTF-Aware Reliability Task Scheduling for PIM-Based Heterogeneous Computing System. 25-30 - Keng-Wei Chang, Chun-Yang Huang, Szu-Pang Mu, Jian-Min Huang, Shi-Hao Chen, Mango C.-T. Chao:
DVFS Binning Using Machine-Learning Techniques. 31-36 - Teresa L. McLaurin:
Periodic Online LBIST Considerations for a Multicore Processor. 37-42 - Venkat Yellapragada, Suresh Raman, Banadappa Shivaray, Luc Romain, Benoit Nadeau-Dostie, Martin Keim, Jean-Francois Cote, Albert Au, Giri Podichetty, Ashok Anbalan:
Implementing Design-for-Test Within a Tile-Based Design Methodology - Challenges and Solutions. 43-48 - Aibin Yan, Zhile Chen, Zhengfeng Huang, Xiangsheng Fang, Maoxiang Yi, Jing Guo:
Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique. 49-54 - Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero:
A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks. 55-60 - Tara Ghasempouri, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik:
An Automatic Approach to Evaluate Assertions' Quality Based on Data-Mining Metrics. 61-66 - Pin-Ru Jhao, Denny C.-Y. Wu, Charles H.-P. Wen:
Skew-Aware Functional Timing Analysis Against Setup Violation for Post-Layout Validation. 67-72 - Ying Wang, Wen Li, Huawei Li, Xiaowei Li:
Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-processors. 73-78 - Jing Ye, Yipei Yang, Yue Gong, Yu Hu, Xiaowei Li:
Grey Zone in Pre-Silicon Hardware Trojan Detection. 79-84 - Ying Zhang, Lu Yu, Huawei Li, Jianhui Jiang:
Small Trojan Testing Using Bounded Model Checking. 85-90 - Tomonori Yanagida, Shohei Shibuya, Kosuke Machida, Koji Asami, Haruo Kobayashi:
Low-Distortion One-Tone and Two-Tone Signal Generation Using AWG Over Full Nyquist Region. 91-96 - Yuming Zhuang, Degang Chen:
Accurate Spectral Testing with Impure Test Stimulus for Multi-tone Test. 97-102 - Yuming Zhuang, Degang Chen:
Cost-Effective High Purity Signal Generator Using Pre-distortion. 103-108 - Guoliang Li, Henry Zhao, Qinfu Yang, Jun Qian, Yu Huang:
Industrial Case Studies of SoC Test Scheduling Optimization by Selecting Appropriate EDT Architectures. 109-114 - Takeru Nishimi, Yasuo Sato, Seiji Kajihara, Yoshiyuki Nakamura:
Good Die Prediction Modelling from Limited Test Items. 115-120 - Kun-Han Tsai:
X-Sources Analysis for Improving the Test Quality. 121-126 - Chih-Hao Wang, Chi-Hsuan Ho, Tong-Yu Hsieh:
Error Indication Signal Collapsing for Implication-Based Concurrent Error Detection. 127-132 - Tong-Yu Hsieh, Chao-Ru Chen:
A No-Reference Error-Tolerability Test Methodology for Image Processing Applications. 133-138 - Behrad Niazmand, Siavoosh Payandeh Azad, Tara Ghasempouri, Jaan Raik, Gert Jervan:
A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers. 139-144 - Xi Chen, Omid Aramoon, Gang Qu, Aijiao Cui:
Balancing Testability and Security by Configurable Partial Scan Design. 145-150 - Chun-Yu Lin, Juinn-Dar Huang, Hailong Yao, Tsung-Yi Ho:
A Comprehensive Security System for Digital Microfluidic Biochips. 151-156
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