default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDISSCC 2008: San Francisco, CA, USA
- 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008. IEEE 2008, ISBN 978-1-4244-2010-0
Evening Sessions
- Jan Sevenhans, Rudolf Koch:
Green Electronics: Environmental Impacts, Power, E-Waste. 12-13 - Christian C. Enz, Ernesto Perea, Ken Cioffi:
MEMS for Frequency Synthesis and Wireless RF Communications (or Life without Quartz Crystal). 14-15
Plenary Session
- Hyung Kyu Lim:
The 2nd Wave of the Digital Consumer Revolution: Challenges and Opportunities! 18-23 - Bill Buxton:
Surface and Tangible Computing, and the "Small" Matter of People and Design. 24-29 - Mike Muller:
Embedded Processing at the Heart of Life and Style. 32-37 - Jeff Hawkins:
Why Can't A Computer Be More Like A Brain? Or What To Do With All Those Transistors? 38-41
Image Sensors & Technology
- Cristiano Niclass, Claudio Favi, Theo Kluter, Marek Gersbach, Edoardo Charbon:
A 128×128 Single-Photon Imager with on-Chip Column-Level 10b Time-to-Digital Converter Array Capable of 97ps Resolution. 44-45 - Dongsoo Kim, Jihyun Cho, Seunghyun Lim, Dongmyung Lee, Gunhee Han:
A 5000S/s Single-Chip Smart Eye-Tracking Sensor. 46-47 - Keith Fife, Abbas El Gamal, H.-S. Philip Wong:
A 3MPixel Multi-Aperture Image Sensor with 0.7μm Pixels in 0.11μm CMOS. 48-49 - Takayoshi Yamada, Shigetaka Kasuga, Takahiko Murata, Yoshihisa Kato:
A 140dB-Dynamic-Range MOS Image Sensor with In-Pixel Multiple-Exposure Synthesis. 50-51 - Yoshitaka Egawa, Nagataka Tanaka, Nobuhiro Kawai, Hiromichi Seki, Akira Nakao, Hiroto Honda, Y. Lida, Makoto Monoi:
A White-RGB CFA-Patterned CMOS Image Sensor with Wide Dynamic Range. 52-53 - K. Kagawau, Sanshiro Shishido, Masahiro Nunoshita, Jun Ohta
:
A 3.6pW/frame·pixel 1.35V PWM CMOS Imager with Dynamic Pixel Readout and no Static Bias Current. 54-55 - Shoji Kawahito, Jong-Ho Park, Keigo Isobe, Suhaidi Shafie, T. Lida, Takashi Mizota:
A CMOS Image Sensor Integrating Column-Parallel Cyclic ADCs with On-Chip Digital Error Correction Circuits. 56-57 - J. Moholt, T. Willassen, John Ladd, Xiaofeng Fan, D. Gans:
A 2Mpixel 1/4-inch CMOS Image Sensor with Enhanced Pixel Architecture for Camera Phones and PC Cameras. 58-59 - Eric G. Stevens, Hirofumi Komori, Hung Doan, Hiroaki Fujita, Jeffery Kyan, Christopher Parks, Gang Shi, Cristian Tivarus, Jian Wu:
Low-Crosstalk and Low-Dark-Current CMOS Image-Sensor Technology Using a Hole-Based Detector. 60-61 - Xinyang Wang, Martijn F. Snoeij, Padmakumar R. Rao, Adri Mierop, Albert J. P. Theuwissen:
A CMOS Image Sensor with a Buried-Channel Source Follower. 62-63
Filters and Amplifiers
- Masaki Kitsunezuka, Shinichi Hori, Tadashi Maeda:
A Widely-Tunable Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio. 66-67 - Atsushi Yoshizawa, Sachio Lida:
A Gain-Boosted Discrete-Time Charge-Domain FIR LPF with Double-Complementary MOS Parametric Amplifiers. 68-69 - Joachim Becker, Fabian Henrici, Stanis Trendelenburg, Maurits Ortmanns, Yiannos Manoli:
A Continuous-Time Hexagonal Field-Programmable Analog Array in 0.13μm CMOS with 186MHz GBW. 70-71 - Stefano D'Amico, Marcello De Matteis, Andrea Baschirotto:
A 6th-Order 100μA 280MHz Source-Follower-Based Single-loop Continuous-Time Filter. 72-73 - J. Frerik Witte, Johan H. Huijsing, Kofi A. A. Makinwa:
A Current-Feedback Instrumentation Amplifier with 5μV Offset for Bidirectional High-Side Current-Sensing. 74-75 - Muhammed Bolatkale, Michiel A. P. Pertijs, Wilko J. Kindt, Johan H. Huijsing, Kofi A. A. Makinwa:
A BiCMOS Operational Amplifier Achieving 0.33μV°C Offset Drift using Room-Temperature Trimming. 76-77 - Daniel Micusik, Horst Zimmermann:
130dB-DR Transimpedance Amplifier with Monotonic Logarithmic Compression and High-Current Monitor. 78-79
Microprocessors
- Marc Tremblay, Shailender Chaudhry:
A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® Processor. 82-83 - Georgios K. Konstadinidis, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar:
Implementation of a Third-Generation 16-Core 32-Thread Chip-Multithreading SPARCs® Processor. 84-85 - Osamu Takahashi, Chad Adams, D. Ault, Erwin Behnen, O. Chiang, Scott R. Cottier, Paula K. Coulman, James Culp, Gilles Gervais, M. S. Gray, Y. Itaka, C. J. Johnson, Fumihiro Kono, L. Maurice, Kevin W. McCullen, Lam Nguyen, Y. Nishino, Hiromi Noro, Jürgen Pille, Mack W. Riley, M. Shen, Chiaki Takano, Shunsako Tokito, Tina Wagner, Hiroshi Yoshihara:
Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI. 86-87 - Shane Bell, Bruce Edwards, John Amann, Rich Conlin, Kevin Joyce, Vince Leung, John MacKay, Mike Reif, Liewei Bao, John F. Brown III, Matthew Mattina, Chyi-Chang Miao, Carl Ramey, David Wentzlaff, Walker Anderson, Ethan Berger, Nat Fairbanks, Durlov Khan, Froilan Montenegro, Jay Stickney, John Zook:
TILE64 - Processor: A 64-Core SoC with Mesh Interconnect. 88-89 - Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara:
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. 90-91 - Blaine A. Stackhouse, Brian S. Cherkauer, Michael K. Gowan, Paul E. Gronowski, Chris Lyles:
A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor. 92-93 - Dan Krueger, Erin Francom, Jack Langsdorf:
Circuit Design for Voltage Scaling and SER Immunity on a Quad-Core Itanium® Processor. 94-95
High-Speed Transceivers
- Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Masayoshi Yagyu, Ryo Nemoto, Takashi Takemoto, Tatsuya Saito, Norio Chujo, Keiichi Yamamoto, Hisaaki Kanai, Atsuhiro Hayashi:
An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane. 98-99 - Chih-Fan Liao, Shen-Iuan Liu:
A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR. 100-101 - Jri Lee, Ming-Shuan Chen, Huaide Wang:
A 20Gb/s Duobinary Transceiver in 90nm CMOS. 102-103 - H. Uchiki, Y. Ota, M. Tani, Yasushi Hayakawa, Katsushi Asahina:
A 6Gb/s RX Equalizer Adapted Using Direct Measurement of the Equalizer Output Amplitude. 104-105 - Sandeep Gupta, José Tellado, Sridhar Begur, Frank Yang, Vishnu Balan, Michael A. Inerfield, Dariush Dabiri, John Dring, Sachin Goel, Kumaraguru Muthukumaraswamy, Frank McCarthy, Glenn Golden, Jiangfeng Wu, Susan Arno, Sanjay Kasturia:
A 10Gb/s IEEE 802.3an-Compliant Ethernet Transceiver for 100m UTP Cable in 0.13μm CMOS. 106-107 - Andrew C. Y. Lin, Marc J. Loinaz:
A Serial Data Transmitter for Multiple 10Gb/s Communication Standards in 0.13μm CMOS. 108-109 - Marcel A. Kossel, Christian Menolfi, Jonas R. M. Weiss, Peter Buchmann, George von Büren, Lucio Rodoni, Thomas Morf, Thomas Toifl, Martin L. Schmatz:
A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS. 110-111 - Hyung-Joon Chi, Jae-Seung Lee, Seong-Hwan Jeon, Seung-Jun Bae, Jae-Yoon Sim, Hong-June Park:
A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration. 112-113
UWB Potpourri
- Murat Demirkan, Richard R. Spencer:
A 1.8Gpulses/s UWB Transmitter in 90nm CMOS. 116-117 - Yuanjin Zheng, M. Annamalai Arasu, King-Wah Wong, Yen Ju The, Andrew Poh Hoe Suan, Duy Duong Tran, Wooi Gan Yeoh, Dim-Lee Kwong:
A 0.18μm CMOS 802.15.4a UWB Transceiver for Communication and Localization. 118-119 - Ta-Shun Chu, Hossein Hashemi:
A CMOS UWB Camera with 7×7 Simultaneous Active Pixels. 120-121 - Oliver Werther, Mark S. Cavin, Angelika Schneider, Robert Renninger, Bo Liang, Long Bu, Yalin Jin, John Marcincavage:
A Fully Integrated 14-Band 3.1-to-10.6GHz 0.13μm SiGe BiCMOS UWB RF Transceiver. 122-123 - Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Stefano Marsili, Christoph Sandner, Andrea Gerosa, Andrea Neviani:
UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking. 124-125 - Tai-You Lu, Wei-Zen Chen:
A 3-to-10GHz 14-Band CMOS Frequency Synthesizer with Spurs Reduction for MB-OFDM UWB System. 126-127 - Remco van de Beek, Jos Bergervoet, Harish Kundur, Domine Leenaerts, Gerard van der Weide:
A 0.6-to-10GHz Receiver Front-End in 45nm CMOS. 128-129 - Stephane Pinel, Saikat Sarkar, Padmanava Sen, Bevin G. Perumana, David Yeh, Debasis Dawn, Joy Laskar:
A 90nm CMOS 60GHz Radio. 130-131 - Namjun Cho, Jeabin Lee, Long Yan, Joonsung Bae, Sunyoung Kim, Hoi-Jun Yoo:
A 60kb/s-to-10Mb/s 0.37nJ/b Adaptive-Frequency-Hopping Transceiver for Body-Area Network. 132-133
TD: Electronics for Life Sciences
- Kazuo Yano, Nobuo Sato, Yoshihiro Wakisaka, Satomi Tsuji, Norio Ohkubo, Miki Hayakawa, Norihiko Moriwaki:
Life Thermoscope: Integrated Microelectronics for Visualizing Hidden Life Rhythm. 136-137 - Alan Chi Wai Wong, Declan McDonagh, Ganesh Kathiresan, Okundu C. Omeni, Omar El-Jamaly, Thomas C.-K. Chan, Paul Paddan, Alison J. Burdett:
A 1V, Micropower System-on-Chip for Vital-Sign Monitoring in Wireless Body Sensor Networks. 138-139 - Yong Liu, Nan Sun, Hakho Lee, Ralph Weissleder, Donhee Ham:
CMOS Mini Nuclear Magnetic Resonance System and its Application for Biomolecular Sensing. 140-141 - Joachim N. Burghartz, Thorsten Engelhardt, Heinz-Gerd Graf, Christine Harendt, Harald Richter, Cor Scherjon, Karsten Warkentin:
CMOS Imager Technologies for Biomedical Applications. 142-143 - Albrecht Rothermel, Volker Wieczorek, Liu Liu, Alfred Stett, Matthias Gerhardt, Alex Harscher, Steffen Kibbel:
A 1600-pixel Subretinal Chip with DC-free Terminals and ±2V Supply Optimized for Long Lifetime and High Stimulation Efficiency. 144-145 - Moo Sung Chae, Wentai Liu, Zhi Yang, Tung-Chien Chen, Jungsuk Kim, Mohanasankar Sivaprakasam, Mehmet R. Yuce:
A 128-Channel 6mW Wireless Neural Recording IC with On-the-Fly Spike Sorting and UWB Tansmitter. 146-147 - Na Lei, Brendon O. Watson, Jason N. MacLean, Rafael Yuste, Kenneth L. Shepard:
A 256x256 CMOS Microelectrode Array for Extracellular Neural Stimulation of Acute Brain Slices. 148-149 - Hyejung Kim, Yongsang Kim, Young-Se Kwon, Hoi-Jun Yoo:
A 1.12mW Continuous Healthcare Monitor Chip Integrated on a Planar Fashionable Circuit Board. 150-151
Evening Sessions
- Satoshi Tanaka, Marc Tiebout, Ali Hajimiri:
From Silicon Aether and Back. 152-153 - Venu Gopinathan, Boris Murmann:
Unusual Data-Converter Techniques. 154-155 - Sreedhar Natarajan, Nicky Lu:
Private Equity: Fight them or Invite them. 156-157 - Johannes Solhusvik, Tim Denison:
Trusting our Lives to Sensors. 158-159
Medical & Displays
- Timothy Denison, Wesley Santa, Randy Jensen, Dave Carlson, Gregory Molnar, Al Avestruz:
An 8μW Heterodyning Chopper Amplifier for Direct Extraction of 2μVrms Neuronal Biomarkers. 162-163 - Refet Firat Yazicioglu, Patrick Merken, Robert Puers, Chris Van Hoof:
A 200μW Eight-Channel Acquisition ASIC for Ambulatory EEG Systems. 164-165 - Bruce Rae, Chris Griffin, Keith R. Muir, John M. Girkin, Erdan Gu, David R. Renshaw, Edoardo Charbon, Martin D. Dawson, Robert K. Henderson:
A Microsystem for Time-Resolved Fluorescence Analysis using CMOS Single-Photon Avalanche Diodes and Micro-LEDs. 166-167 - Flavio Heer, Manuel Keller, George Yu, Jiri Janata, Mira Josowicz, Andreas Hierlemann:
CMOS Electro-Chemical DNA-Detection Array with On-Chip ADC. 168-169 - Toshishige Shimamura, Hiroki Morimura, Nobuhiro Shimoyama, Tomomi Sakata, Satoshi Shigematsu, Katsuyuki Machida, Mamoru Nakanishi:
A Fingerprint Sensor with Impedance Sensing for Fraud Detection. 170-171 - Iliana Fujimori-Chen, Rikky Muller, W. Kan, Matt Fazio, A. Farrell, David H. Whitney:
A 10b 75ns CMOS Scanning-Display-Driver System for QVGA LCDs. 172-173 - Jinyong Jeon, Yong-Joon Jeon, Young-Suk Son, Kwang-Chan Lee, Hyung-Min Lee, Seungchul Jung, Kang-Ho Lee, Gyu-Hyeong Cho:
A Direct-Type Fast Feedback Current Driver for Medium-to Large-Size AMOLED Displays. 174-175 - Yoon-Kyung Choi, Zhong-Yuan Wu, KyungMyun Kim, Yong Hun Lee, Min-Soo Cho, Hyo-Sun Kim, Dong-Hun Lee, Won-Gab Jung:
A Compact Low-Power CDAC Architecture for Mobile TFT-LCD Driver ICs. 176-177
mm-Wave & Phased Arrays
- Ekaterina Laskin, Mehdi Khanpour, Ricardo Andres Aroca, Keith K. W. Tang, Patrice Garcia, Sorin P. Voinigescu:
A 95GHz Receiver with Fundamental-Frequency VCO and Static Frequency Divider in 65nm Digital CMOS. 180-181 - Bagher Afshar, Yanjie Wang, Ali M. Niknejad:
A Robust 24mW 60GHz Receiver in 90nm Standard CMOS. 182-183 - Karen Scheir, Stephane Bronckers, Jonathan Borremans, Piet Wambacq, Yves Rolain:
A 52GHz Phased-Array Receiver Front-End in 90nm Digital CMOS. 184-185 - Sanggeun Jeon, Yu-Jiu Wang, Hua Wang, Florian Bohn, Arun Natarajan, Aydin Babakhani, Ali Hajimiri:
A Scalable 6-to-18GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS. 186-187 - Aydin Babakhani, David B. Rutledge, Ali Hajimiri:
A Near-Field Modulation Technique Using Antenna Reflector Switching. 188-189 - Ali Parsa, Behzad Razavi:
A 60GHz CMOS Receiver Using a 30GHz LO. 190-191 - Christopher Weyers, Pierre Mayr, Johannes W. Kunze, Ulrich Langmann:
A 22.3dB Voltage Gain 6.1dB NF 60GHz LNA in 65nm CMOS with Differential Output. 192-193 - Yiqun Cao, Vadim Issakov, Marc Tiebout:
A 2kV ESD-Protected 18GHz LNA with 4dB NF in 0.13μm CMOS. 194-195 - Amin Arbabian, Ali M. Niknejad:
A Broadband Distributed Amplifier with Internal Feedback Providing 660GHz GBW in 90nm CMOS. 196-197
Cellular Transceivers
- Hsiang-Hui Chang, Ping-Ying Wang, Jing-Hong Conan Zhan, Bing-Yu Hsieh:
A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE. 200-201 - Bernard Tenbroek, Jon Strange, Dimitris Nalbantis, Christopher Jones, Paul Fowers, Steve Brett, Christophe Beghein, Federico Beffa:
Single-Chip Tri-Band WCDMA/HSDPA Transceiver without External SAW Filters and with Integrated TX Power Control. 202-203 - Edward A. Keehr, Ali Hajimiri:
Equalization of IM3 Products in Wideband Direct-Conversion Receivers. 204-205 - Hooman Darabi, Alireza Zolfaghari, Henrik Jensen, John C. Leete, Behnam Mohammadi, Janice Chiu, Tom Li, Zhimin Zhou, Paul Lettieri, Yuyu Chang, Amir Hadji-Abdolhamid, Paul Chang, Mohammad Nariman, Iqbal Bhatti, Ali Medi, Louie Serrano, Jared Welz, Kambiz Shoarinejad, S. M. Shajedul Hasan, Jesse Castaneda, Jay Kim, Huey Tran, Patrick Kilcoyne, R. Chen, Bobby Lee, Barry Zhao, Brima Ibrahim, Maryam Rofougaran, Ahmadreza Rofougaran:
A Fully Integrated Quad-Band GPRS/EDGE Radio in 0.13μm CMOS. 206-207 - Robert Bogdan Staszewski, Dirk Leipold, Oren E. Eliezer, Mitch Entezari, Khurram Muhammad, Imran Bashir, Chih-Ming Hung, John L. Wallberg, Roman Staszewski, Patrick Cruise, Sameh Rezeq, Sudheer K. Vemulapalli, Khurram Waheed, Nathen Barton, Meng-Chang Lee, Chan Fernando, Kenneth Maggio, Tom Jung, Imtinan Elahi, S. Larson, Thomas Murphy, Gennady Feygin, Irene Yuanying Deng, Terry Mayhugh Jr., Yo-Chuol Ho, K.-M. Low, Charles Lin, J. Jaehnig, J. Kerr, Jaimin Mehta, S. Glock, T. Almholt, Sumeer Bhatara:
A 24mm2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS. 208-209 - Giuseppe Li Puma, Ernst Kristan, Paolo De Nicola, Cyril Vannier, Braam Greyling, Salvatore Piccolella:
Integration of a SiP for GSM/EDGE in CMOS Technology. 210-211 - Ahmad Mirzaei, Hooman Darabi:
A Low-Power WCDMA Transmitter with an Integrated Notch Filter. 212-213 - Shouhei Kousai, Daisuke Miyashita, Junji Wadatsumi, Asuka Maki, Takahiro Sekiguchi, Rui Ito, Mototsugu Hamada:
A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power Amplifier. 214-215 - Andrea Mazzanti, Marco Sosio, Matteo Repossi, Francesco Svelto:
A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS. 216-217
Optical Communication
- Tine De Ridder, Peter Ossieur, B. Baekelandt, Cedric Mélange, Johan Bauwelinck, Colin Ford, Xing-Zhi Qiu, Jan Vandewege:
A 2.7V 9.8Gb/s Burst-Mode TIA with Fast Automatic Gain Locking and Coarse Threshold Extraction. 220-221 - Chia-Ming Tsai, Mao-Cheng Chiu:
A 10Gb/s Laser-Diode Driver with Active Back-Termination in 0.18μm CMOS. 222-223 - Che-Fu Liang, Shen-Iuan Liu:
A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode Cells. 224-225 - Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo:
A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DAC. 226-227 - Hidemi Noguchi, Nobuhide Yoshida, Hiroaki Uchida, Manabu Ozaki, Shunichi Kanemitsu, Shigeki Wada:
A 40Gb/s CDR with Adaptive Decision-Point Control Using Eye-Opening-Monitor Feedback. 228-229 - Sushmit Goswami, Tino Copani, Anuj Jain, Habib Karaki, Bert Vermeire, Hugh J. Barnaby, Gregory J. Fetzer, Rick Vercillo, Sayfe Kiaei:
A 96Gb/s-Throughput Transceiver for Short-Distance Parallel Optical Links. 230-231 - Oscar E. Agazzi, Diego E. Crivelli, Mario Rafael Hueda, Hugo S. Carrer, German C. Luna, Ali Nazemi, Carl R. Grace, Bilal Kobeissy, Cindra Abidin, Mohammad Kazemi, Mahyar Kargar, César Marquez, Sumant Ramprasad, Federico Bollo, Vladimir A. Posse, Stephen Wang, Georgios Asmanis, George Eaton, Norman Swenson, Tom Lindsay, Paul Voois:
A 90nm CMOS DSP MLSD Transceiver with Integrated AFE for Electronic Dispersion Compensation of Multi-mode Optical Fibers at 10Gb/s. 232-233 - Hyeon-Min Bae, Andrew C. Singer, Jonathan B. Ashbrook, Naresh R. Shanbhag:
A 10Gb/s MLSE-based Electronic-Dispersion-Compensation IC with Fast Power-Transient Management for WDM Add/Drop Networks. 234-235
High-Efficiency Data Converters
- Vito Giannini, Pierluigi Nuzzo, Vincenzo Chironi, Andrea Baschirotto, Geert Van der Plas, Jan Craninckx:
An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS. 238-239 - Brian P. Ginsburg, Anantha P. Chandrakasan:
Highly Interleaved 5b 250MS/s ADC with Redundant Channels in 65nm CMOS. 240-241 - Geert Van der Plas, Bob Verbruggen:
A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC. 242-243 - Michiel van Elzakker, Ed van Tuijl, Paul F. J. Geraedts, Daniël Schinkel, Eric A. M. Klumperink, Bram Nauta:
A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC. 244-245 - Andrea Agnes, Edoardo Bonizzoni, Piero Malcovati, Franco Maloberti:
A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator. 246-247 - Byung Geun Lee, Byung-Moo Min, Gabriele Manganaro, Jonathan W. Valvano:
A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC. 248-249 - Mounir Boulemnakher, Eric Andre, Jocelyn Roux, Frédéric Paillardet:
A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS. 250-251 - Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas:
A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS. 252-253
Mobile Processing
- Gianfranco Gerosa, Steve Curtis, Michael D'Addeo, Bo Jiang, Belliappa Kuttanna, Feroze Merchant, Binta Patel, Mohammed H. Taufique, Haytham Samarchi:
A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-Κ Metal Gate CMOS. 256-257 - Gordon Gammie, Alice Wang, Minh Chau, Sumanth Gururajarao, Robert Pitts, Fabien Jumel, Stacey Engel, Philippe Royannez, Rolf Lagerquist, Hugh Mair, Jeff Vaccani, Greg Baldwin, Keerthi Heragu, Rituparna Mandal, Michael Clinton, Don Arden, Uming Ko:
A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques. 258-259 - Masao Naruse, Tatsuya Kamei, Toshihiro Hattori, Takahiro Irita, Kenichi Nitta, Takao Koike, Shinichi Yoshioka, Koji Ohno, Masahito Saigusa, Minoru Sakata, Yukio Kodama, Yuji Arai, Teruyoshi Komuro:
A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU. 260-261 - Shuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, Chen Kong Teh, Hiroyuki Usui, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Hiroyuki Hara, Takahiro Yamashita, Jun Tanabe, Masaru Uchiyama, Yoshiro Tsuboi, Takashi Miyamori, Takeshi Kitahara, Hironori Sato, Y. Homma, Shuuji Matsumoto, Keiko Seki, Y. Watanabe, Mototsugu Hamada, Makoto Takahashi:
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. 262-263 - Christian Benkeser, Andreas Burg, Teo Cupaiuolo, Qiuting Huang:
A 58mW 1.2mm2 HSDPA Turbo Decoder ASIC in 0.13μm CMOS. 264-265 - Anders Nilsson, Eric Tell, Dake Liu:
An 11mm2 70mW Fully-Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12μm CMOS. 266-267
Embedded & Graphics DRAMs
- Sergey Romanovsky, Atul Katoch, Arun Achyuthan, C. O'Connell, Sreedhar Natarajan, C. Huang, Chuan-Yu Wu, Min-Jer Wang, C. J. Wang, P. Chen, R. Hsieh:
A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS. 270-271 - Kim Hardee, Michael Parris, O. Fred Jones, Doug Butler, Mike Mound, G. W. Jones, Tim Egging, Tomofumi Arakawa, Katsuhiko Sasahara, Kazuo Taniguchi, Masayuki Miyabayashi:
A 170GB/s 16Mb Embedded DRAM with Data-Bus Charge-Recycling. 272-273 - Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi:
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. 274-275 - Mariko Kaku, Hitoshi Iwai, Takeshi Nagai, Masaharu Wada, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Takayuki Iwai, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano, Nobuaki Otsuka:
An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications. 276-277 - Seung-Jun Bae, Young-Soo Sohn, Kwang-Il Park, Kyoung-Ho Kim, Dae-Hyun Chung, Jingook Kim, Si-Hong Kim, Min-Sang Park, Jae-Hyung Lee, Sam-Young Bang, Ho-Kyung Lee, In-Soo Park, Jae-Sung Kim, Dae-Hyun Kim, Hye-Ran Kim, Yong-Jae Shin, Cheol-Goo Park, Gil-Shin Moon, Ki-Woong Yeom, Kang-Young Kim, Jae-Young Lee, Hyang-Ja Yang, Seong-Jin Jang, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim:
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques. 278-279 - Dong-Uk Lee, Shin-Deok Kang, Nak-Kyu Park, Hyun-Woo Lee, Young-Kyoung Choi, Jung-Woo Lee, Seung-Wook Kwack, Hyeong-Ouk Lee, Won-Joo Yun, Sang-Hoon Shin, Kwan-Weon Kim, Young-Jung Choi, Ye Seok Yang:
Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface. 280-281 - Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Shin-Deok Kang, Ji-Yeon Yang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyang-Hwa Choi, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Young-Kyoung Choi, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Ye Seok Yang:
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology. 282-283
TD: Trends in Signal and Power Transmission
- S. Robinet, B. Gomez, N. Delorme:
A CMOS-SOI 2.45GHz Remote-Powered Sensor Tag. 286-287 - Albert Missoni, Christian Klapf, Wolfgang Pribyl, Günter Hofer, Gerald Holweg:
A Triple-Band Passive RFID Tag. 288-289 - Kris Myny, Steven Van Winckel, Soeren Steudel, Peter Vicca, Stijn De Jonge, Monique J. Beenhakkers, C. W. Sele, Nick A. J. M. van Aerle, Gerwin H. Gelinck, Jan Genoe, Paul Heremans:
An Inductively-Coupled 64b Organic RFID Tag Operating at 13.56MHz with a Data Rate of 787b/s. 290-291 - Lechang Liu, Makoto Takamiya, Tsuyoshi Sekitani, Yoshiaki Noguchi, Shintaro Nakano, Koichiro Zaitsu, Tadahiro Kuroda, Takao Someya, Takayasu Sakurai:
A 107pJ/b 100kb/s 0.18μm Capacitive-Coupling Transceiver for Printable Communication Sheet. 292-293 - Clint Schow, Fuad E. Doany, Chen Chen, Alexander V. Rylyakov, Christian W. Baks, Daniel M. Kuchta, Richard A. John, Jeffrey A. Kash:
A ≪5mW/Gb/s/link, 16×10Gb/s Bi-Directional Single-Chip CMOS Optical Transceiver for Board-Level Optical Interconnects. 294-295 - Marnix Tack, Peter Moens, Renaud Gillon, Johan Janssens, Stefan Van Roeyen, Jan Sevenhans:
Next Generation Smart Power Technologies - Challenges and Innovations Enabling Complex SoC Integration. 296-297 - Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
An 11Gb/s Inductive-Coupling Link with Burst Transmission. 298-299 - Inge Doms, Patrick Merken, Robert P. Mertens, Chris Van Hoof:
Capacitive Power-Management Circuit for Micropower Thermoelectric Generators with a 2.1μW Controller. 300-301 - Nathaniel J. Guilar, Rajeevan Amirtharajah, Paul J. Hurst:
A Full-Wave Rectifier for Interfacing with Multi-Phase Piezoelectric Energy Harvesters. 302-303
Low-Power Digital
- Chih-Chi Cheng, Chia-Hua Lin, Chung-Te Li, Samuel C. Chang, Chia-Jung Hsu, Liang-Gee Chen:
iVisual: An Intelligent Visual Sensor SoC with 2790fps CMOS Image Sensor and 205GOPS/W Vision Processor. 306-307 - Kwanho Kim, Seungjin Lee, Joo-Young Kim, Minsu Kim, Donghyun Kim, Jeong-Ho Woo, Hoi-Jun Yoo:
A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired Visual-Attention Engine. 308-309 - Pascal Urard, L. Paumier, V. Heinrich, N. Raina, Nitin Chawla:
A 360mW 105Mb/s DVB-S2 Compliant Codec based on 64800b LDPC and BCH Codes enabling Satellite-Transmission Portable Devices. 310-311 - Sumito Arakawa, Yuji Yamaguchi, Satoshi Akui, Yasushi Fukuda, Hirofumi Sumi, Hiroshi Hayashi, Masahiro Igarashi, Kei Ito, Hidetoshi Nagano, Masatoshi Imai, Naosuke Asari:
A 512GOPS Fully-Programmable Digital Image Processor with full HD 1080p Processing Capabilities. 312-313 - Yu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu, Wei-Cheng Tai, Wei-Cheng Chang, Tian-Sheuan Chang:
A 242mW 10mm2 1080p H.264/AVC High-Profile Encoder Chip. 314-315 - Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS. 316-317 - Joyce Kwong, Yogesh K. Ramadass, Naveen Verma, Markus Koesler, Korbinian Huber, Hans Moormann, Anantha P. Chandrakasan:
A 65nm Sub-Vt Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC Converter. 318-319
Wideband Receivers
- Zhiyu Ru, Eric A. M. Klumperink, Bram Nauta:
A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection. 322-323 - Jonathan Borremans, Stephane Bronckers, Piet Wambacq, Maarten Kuijk, Jan Craninckx:
A Single-Inductor Dual-Band VCO in a 0.06mm2 5.6GHz Multi-Band Front-End in 90nm Digital CMOS. 324-325 - Stephan C. Blaakmeer, Eric A. M. Klumperink, Domine Leenaerts, Bram Nauta:
A Wideband Balun LNA I/Q-Mixer combination in 65nm CMOS. 326-327
TD: MOS Medley
- Hiroyuki Kawanishi, Kuniyuki Hishinuma, Masahisa Kimura, Noboru Motai, Yoshinori Soutome, Tomoyuki Tsukii, Yasuhisa Ishikawa, Toshishige Katai, Natsuki Hashiba:
64/256-Element Thermopile, Infrared Sensor Chip with 4 Built-In Amplifiers for use in Atmospheric Pressure Conditions. 330-331 - Éric Colinet, Cedric Durand, Patrick Audebert, Philippe Renaux, Denis Mercier, Laurent Duraffourg, Eric Ollier, Fabrice Casset, Pascal Ancey, Lionel Buchaillot, Adrian M. Ionescu:
Measurement of Nano-Displacement Based on In-Plane Suspended-Gate MOSFET Detection Compatible with a Front-End CMOS Process. 332-333 - Horst Rempp, Joachim N. Burghartz, Christine Harendt, Nicoleta Pricopi, Marcus Pritschow, Christian Reuter, Harald Richter, Inge Schindler, Martin Zimmermann:
Ultra-Thin Chips on Foil for Flexible Electronics. 334-335 - Nasim Nikkhoo, Cintia Man, Karen Maxwell, P. Glenn Gulak:
A 0.18μm CMOS Integrated Sensor for the Rapid Identification of Bacteria. 336-337
PLLs & Oscillators
- Chun-Ming Hsu, Matthew Z. Straayer, Michael H. Perrott:
A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation. 340-341 - Kevin J. Wang, Ashok Swaminathan, Ian Galton:
Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL. 342-343 - Colin Weltin-Wu, Enrico Temporiti, Daniele Baldi, Francesco Svelto:
A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction. 344-345 - Xueyi Yu, Yuanfeng Sun, Li Zhang, Woogeun Rhee, Zhihua Wang:
A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering. 346-347 - Paul F. J. Geraedts, Ed van Tuijl, Eric A. M. Klumperink, Gerard Wienk, Bram Nauta:
A 90μW 12MHz Relaxation Oscillator with a -162dB FOM. 348-349 - Michael S. McCorquodale, Scott M. Pernia, Justin D. O'Day, Gordon A. Carichner, Eric D. Marsman, Nam Nguyen, Sundus Kubba, Si Nguyen, Jonathan J. Kuhn, Richard B. Brown:
A 0.5-to-480MHz Self-Referenced CMOS Clock Generator with 90ppm Total Frequency Error and Spread-Spectrum Capability. 350-351 - Shayan Farahvash, Chee Quek, Monica Mak:
A Temperature-Compensated Digitally-Controlled Crystal Pierce Oscillator for Wireless Applications. 352-353
WLAN/WPAN
- Ofir Degani, Mark Ruberto, Emanuel Cohen, Yishai Eilat, Benjamin Jann, Fabian Cossoy, Nikolay Telzhensky, Tzvi Maimon, Gregory Normatov, Rotem Banin, Ori Ashkenazi, Assaf Ben Bassat, Sharon Zaguri, Gabriel Hara, Mario Zajac, Eyal Shaviv, Shay Wail, Amir Fridman, Richard Lin, Shai Gross:
A 1×2 MIMO Multi-Band CMOS Transceiver with an Integrated Front-End in 90nm CMOS for 802.11a/g/n WLAN Applications. 356-357 - Lalitkumar Nathawad, Masoud Zargari, Hirad Samavati, Srenik S. Mehta, Alireza Kheirkhahi, Phoebe Chen, Ke Gong, Babak Vakili-Amini, Justin A. Hwang, Mike Shuo-Wei Chen, Manolis Terrovitis, Brian J. Kaczynski, Sotirios Limotyrakis, Michael P. Mack, Haitao Gan, MeeLan Lee, Shahram Abdollahi-Alibeik, Burcin Baytekin, Keith Onodera, Sunetra Mendis, Andrew Chang, Steve H. Jen, David K. Su, Bruce A. Wooley:
A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN. 358-359 - Andras Pozsgay, Tommy Zounes, Razak Hossain, Mounir Boulemnakher, Vincent Knopik, Sébastien Grange:
A Fully Digital 65nm CMOS Transmitter for the 2.4-to-2.7GHz WiFi/WiMAX Bands using 5.4GHz ΔΣ RF DACs. 360-361 - Franck Montaudon, Rayan Mina, Stéphane Le Tual, Loic Joët, Daniel Saias, Razak Hossain, Florent Sibille, Christian Corre, Valerie Carrat, Emmanuel Chataigner, Jerome Lajoinie, Sébastien Dedieu, Frédéric Paillardet, Ernesto Perea:
A Scalable 2.4-to-2.7GHz Wi-Fi/WiMAX Discrete-Time Receiver in 65nm CMOS. 362-363 - David Weber, William W. Si, Shahram Abdollahi-Alibeik, MeeLan Lee, Richard Chang, Hakan Dogan, Susan Luschas, Paul J. Husted:
A Single-Chip CMOS Radio SoC for v2.1 Bluetooth Applications. 364-365 - Ajay Balankutty, Shih-An Yu, Yiping Feng, Peter R. Kinget:
A 0.6V 32.5mW Highly Integrated Receiver for 2.4GHz ISM-Band Applications. 366-367 - Manuel Camus, Benoit Butaye, Luc Garcia, Mathilde Sié, Bruno Pellat, Thierry Parra:
A 5.4mW 0.07mm2 2.4GHz Front-End Receiver in 90nm CMOS for IEEE 802.15.4 WPAN. 368-369 - Antonio Liscidini, Marika Tedeschi, Rinaldo Castello:
A 2.4 GHz 3.6mW 0.35mm2 Quadrature Front-End RX for ZigBee and WPAN Applications. 370-371 - Adrian Maxim, Ramin Khoini-Poorfard, Mitchell Reid, James T. Kao, Charles D. Thompson, Richard A. Johnson:
A DDFS Driven Mixing-DAC with Image and Harmonic Rejection Capabilities. 372-373
SRAM
- Fatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr:
A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology. 376-377 - Harold Pilo, Vaidyanathan Ramadurai, Geordie Braceras, John A. Gabric, Steve Lamphier, Yue Tan:
A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management. 378-379 - Naveen Verma, Anantha P. Chandrakasan:
A High-Density 45nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing. 380-381 - Atsushi Kawasumi, Tomoaki Yabe, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Akihito Tohata, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Nobuaki Otsuka:
A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-×-ratio Memory Cell. 382-383 - Masanao Yamaoka, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada:
65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS. 384-385 - Kyomin Sohn, Young-Ho Suh, Young-Jae Son, Daesik Yim, Kang-Young Kim, Dae-Gi Bae, Ted Kang, Hoon Lim, Soon-Moon Jung, Hyun-Geun Byun, Young-Hyun Jun, Kinam Kim:
A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy. 386-387 - Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy:
A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS. 388-389 - Chao-Ching Wang, Chieh-Jen Cheng, Tien-Fu Chen, Jinn-Shyan Wang:
An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices. 390-391
Evening Sessions
- Albert Theuwissen, Roland Thewes, Ernesto Perea:
Highlights of IEDM 2007. 392-393 - Yuriy M. Greshishchev, Takuji Yamamoto, Naresh R. Shanbhag:
Trends and Challenges in Optical Communications Front-End. 394-395 - Thucydides Xanthopoulos, Don Draper:
Can Multicore Integration Justify the Increased Cost of Process Scalling? 396-397
Variation Compensation & Measurement
- David T. Blaauw, Sudherssen Kalaiselvan, Kevin Lai, Wei-Hsiang Ma, Sanjay Pant, Carlos Tokunaga, Shidhartha Das, David M. Bull:
Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance. 400-401 - Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De:
Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance. 402-403 - Xiaoyao Liang, David M. Brooks, Gu-Yeon Wei:
A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency. 404-405 - Gregory Uhlmann, Tony Aipperspach, Toshiaki Kirihata, K. Chandrasekharan, Yan Zun Li, Chris Paone, Brian Reed, Norman Robson, John Safran, David Schmitt, Subramanian S. Iyer:
A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS. 406-407 - Fabian Klass, Ashish Jain, Greg Hess, Brian Park:
An All-Digital On-Chip Process-Control Monitor for Process-Variability Measurements. 408-409 - Eric Karl, Prashant Singh, David T. Blaauw, Dennis Sylvester:
Compact In-Situ Sensors for Monitoring Negative-Bias-Temperature-Instability Effect and Oxide Degradation. 410-411 - Rahul M. Rao, Keith A. Jenkins, Jae-Joon Kim:
A Completely Digital On-Chip Circuit for Local-Random-Variability Measurement. 412-413 - Mari Matsumoto, Shinichi Yasuda, Ryuji Ohba, Kazutaka Ikegami, Tetsufumi Tanamoto, Shinobu Fujita:
1200μm2 Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application. 414-415 - Sanjay Pant, David T. Blaauw:
A Charge-Injection-Based Active-Decoupling Technique for Inductive-Supply-Noise Suppression. 416-417
Non-Volatile Memory
- Raul Cernea, Long Pham, Farookh Moogat, Siu Lung Chan, Binh Le, Yan Li, Shouchang Tsao, Taiyuan Tseng, Khanh Nguyen, Jason Li, Jayson Hu, Jong Park, Cynthia Hsu, Fanglin Zhang, Teruhiko Kamei, Hiroaki Nasu, Phil Kliza, Khin Htoo, Jeffery Lutze, Yingda Dong, Masaaki Higashitani, Junhui Yang, Hung-Szu Lin, Vamshi Sakhamuri, Alan Li, Feng Pan, Sridhar Yadala, Subodh Taigor, Kishan Pradhan, James Lan, Jim Chan, Takumi Abe, Yasuyuki Fukuda, Hideo Mukai, Koichi Kawakami, Connie Liang, Tommy Ip, Shu-Fen Chang, Jaggi Lakshmipathi, Sharon Huynh, Dimitris Pantelakis, Mehrdad Mofidi, Khandker Quader:
A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm. 420-421 - Ran Sahar, Avi Lavan, Eran Geyari, Amit Berman, Itzic Cohen, Ori Tirosh, Kobi Danon, Yair Sofer, Yoram Betser, Amichai Givant, Alexander Kushnarenko, Yaal Horesh, Ron Eliyahu, Eduardo Maayan, Boaz Eitan, Wang Pei Jen, Yan Feng, Lin Ching Yao, Kwon Yi Jin, Kwon Sung Woo, Cai En Jing, Yi Jing Jing, Kim Jong Oh, Yi Guan Jiun:
A 4b/Cell 8Gb NROM Data-Storage Memory with Enhanced Write Performance. 422-423 - Johnny Javanifard, Tris Tanadi, Hari Giduturi, Kim Loe, Robert L. Melcher, Shahnam Khabiri, Nicholas T. Hendrickson, Andrew D. Proescholdt, David A. Ward, Mark A. Taylor:
A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed. 424-425 - Dean Nobunaga, Ebrahim Abedifard, Frankie Roohparvar, June Lee, Erwin Yu, Allahyar Vahidimowlavi, Michael Abraham, Sanjay Talreja, Rajesh Sundaram, Rod Rozman, Luyen Vu, Chih-Liang Chen, Uday Chandrasekhar, Rupinder Bains, Vimon Viajedor, William Mak, Munseork Choi, Darshak Udeshi, Michelle Luo, Shahid Qureshi, Jeffrey Tsai, Frederick Jaffin, Yujiang Liu, Marco Mancinelli:
A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface. 426-527 - Ferdinando Bedeschi, Rich Fackenthal, Claudio Resta, Enzo Michele Donzè, Meenatchi Jagasivamani, Egidio Cassiodoro Buda, Fabio Pellizzer, David W. Chow, Alessandro Cabrini, Giacomo Matteo Angelo Calvi, Roberto Faravelli, Andrea Fantini, Guido Torelli, Duane Mills, Roberto Gastaldi, Giulio Casagrande:
A Multi-Level-Cell Bipolar-Selected Phase-Change Memory. 428-429 - Kazushige Kanda, Masaru Koyanagi, Toshio Yamamura, Koji Hosono, Masahiro Yoshihara, Toru Miwa, Yosuke Kato, Alex Mak, Siu Lung Chan, Frank Tsai, Raul Cernea, Binh Le, Eiichi Makino, Takashi Taira, Hiroyuki Otake, Norifumi Kajimura, Susumu Fujimura, Yoshiaki Takeuchi, Mikihiko Itoh, Masanobu Shirakawa, Dai Nakamura, Yuya Suzuki, Yuki Okukawa, Masatsugu Kojima, Kazuhide Yoneya, Takamichi Arizono, Toshiki Hisada, Shinji Miyamoto, Mitsuhiro Noguchi, Toshitake Yaegashi, Masaaki Higashitani, Fumitoshi Ito, Teruhiko Kamei, Gertjan Hemink, Tooru Maruyama, Kazumi Ino, Shigeo Ohshima:
A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology. 430-431
Analog Power Techniques
- Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio:
A 1.2mW 1.6Vpp-Swing Class-AB 16Ω Headphone Driver Capable of Handling Load Capacitance up to 22nF. 434-435 - Srini Ramaswamy, J. Krishnan, Brett Forejt, J. Joy, M. Burns, Gangadhar Burra:
A High-Performance Digital-Input Class-D Amplifier with Direct Battery Connection in a 90nm Digital CMOS Process. 436-437 - Hong-Wei Huang, Chun-Yu Hsieh, Ke-Horng Chen, Sy-Yen Kuo:
A 1V 16.9ppm/°C 250nA Switched-Capacitor CMOS Voltage Reference. 438-439 - Tsz Yin Man, Philip K. T. Mok, Mansun Chan:
An Auto-Selectable-Frequency Pulse-Width Modulator for Buck Converters with Improved Light-Load Efficiency. 440-441 - Yat-Hei Lam, Wing-Hung Ki:
A 0.9V 0.35 μm Adaptively Biased CMOS LDO Regulator with Fast Transient Response. 442-443 - Massimiliano Belloni, Edoardo Bonizzoni, Eduardas Kiseliovas, Piero Malcovati, Franco Maloberti, Tero Peltola, Tomi Teppo:
A 4-Output Single-Inductor DC-DC Buck Converter with Self-Boosted Switch Drivers and 1.2A Total Output Current. 444-445 - Young-Jin Woo, Hanh-Phuc Le, Gyu-Ha Cho, Gyu-Hyeong Cho, Seong-Il Kim:
Load-Independent Control of Switching DC-DC Converters with Freewheeling Current Feedback. 446-447 - Wing-Yee Chu, Bertan Bakkaloglu, Sayfe Kiaei:
A 10MHz-Bandwidth 2mV-Ripple PA-Supply Regulator for CDMA Transmitters. 448-449
Building Blocks for High-Speed Transceivers
- Frank O'Mahony, Sudip Shekhar, Mozhgan Mansuri, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Bryan Casper, David J. Allstot, Randy Mooney:
A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS. 452-453 - Sander Gierkink:
An 800MHz -122dBc/Hz-at-200kHz Clock Multiplier based on a Combination of PLL and Recirculating DLL. 454-455 - Tomoaki Kawamura, Yusuke Ohtomo, Kazuyoshi Nishimura, Noboru Ishihara:
A 1ps-Resolution 2ns-Span 10Gb/s Data-Timing Generator with Spectrum Conversion. 456-457 - Kyu-Hyoun Kim, Paul W. Coteus, Daniel M. Dreps, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman:
A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator. 458-459 - Daeik D. Kim, Jonghae Kim, Choongyeun Cho:
A 94GHz Locking Hysteresis-Assisted and Tunable CML Static Divider in 65nm SOI CMOS. 460-461 - Dirk Pfaff, Sivakumar Kanesapillai, Volodymyr Yavorskyy, Carlos Carvalho, Reza Yousefi, Muhammad Ali Khan, Trevor Monson, Mark Ayoub, Claus Reitlingshoefer:
A 1.8W 115Gb/s Serial Link for Fully Buffered DIMM with 2.1ns Pass-Through Latency in 90nm CMOS. 462-463 - Keith Findlater, Toby Bailey, Adria Bofill, Neil C. Calder, Seyed Danesh, Robert K. Henderson, William Holland, Jed Hurwitz, Steven Maughan, Alasdair Sutherland, Ewan Watt:
A 90nm CMOS Dual-Channel Powerline Communication AFE for Homeplug AV with a Gb Extension. 464-465 - Kun-Hung Tsai, Lan-Chou Cho, Jia-Hao Wu, Shen-Iuan Liu:
3.5mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology. 466-467 - Ankur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei:
An 8×3.2Gb/s Parallel Receiver with Collaborative Timing Recovery. 468-469
Wireless Frequency Generation
- Eunyoung Seok, Changhua Cao, Dongha Shim, Daniel J. Arenas, David B. Tanner, Chih-Ming Hung, Kenneth K. O:
A 410GHz CMOS Push-Push Oscillator with an On-Chip Patch Antenna. 472-473 - Andrea Mazzanti, Pietro Andreani:
A 1.4mW 4.90-to-5.65GHz Class-C CMOS VCO with an Average FoM of 194.5dBc/Hz. 474-475 - Daquan Huang, Tim R. LaRocca, Lorene Samoska, Andy Fung, M.-C. Frank Chang:
324GHz CMOS Frequency Generator Using Linear Superposition Technique. 476-477 - Pierre Vincent, Jean-Baptiste David, Ioan Burciu, Jérôme Prouvée, Christophe Billard, Christine Fuchs, Guy Parat, Emeric Defoucaud, Alexandre Reinhardt:
A 1V 220MHz-Tuning-Range 2.2GHz VCO Using a BAW Resonator. 478-479 - Wei L. Chan, John R. Long, John J. Pekarik:
A 56-to-65GHz Injection-Locked Frequency Tripler with Quadrature Outputs in 90nm CMOS. 480-481 - Yusuke Wachi, Toshiyuki Nagasaku, Hiroshi Kondoh:
A 28GHz Low-Phase-Noise CMOS VCO Using an Amplitude-Redistribution Technique. 482-483 - Stefano Pellerano, Rajarshi Mukhopadhyay, Ashoke Ravi, Joy Laskar, Yorgos Palaskas:
A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS. 484-485
ΔΣ Data Converters
- Khiem Nguyen, Abhishek Bandyopadhyay, Bob Adams, Karl Sweetland, Paul Baginski:
A 108dB SNR 1.1mW Oversampling Audio DAC with a Three-Level DEM Technique. 488-489 - Youngcheol Chae, Inhee Lee, Gunhee Han:
A 0.7V 36μW 85dB-DR Audio ΔΣ Modulator Using Class-C Inverter. 490-491 - Robert H. M. van Veldhoven, Robert Rutten, Lucien J. Breems:
An Inverter-Based Hybrid ΔΣ Modulator. 492-493 - Kyehyung Lee, Jeongseok Chae, Mitsuru Aniya, Koichi Hamashita, Kaoru Takasuka, Seiji Takeuchi, Gabor C. Temes:
A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR. 494-495 - Pukar Malla, Hasnain Lakdawala, Kevin T. Kornegay, Krishnamurthy Soumyanath:
A 28mW Spectrum-Sensing Reconfigurable 20MHz 72dB-SNR 70dB-SNDR DT ΔΣ ADC for 802.11n/WiMAX Receivers. 496-497 - Wenhua Yang, William Schofield, Hajime Shibata, Sudhir Korrapati, Ali Shaikh, Nazmy Abaskharoun, Dave Ribner:
A 100mW 10MHz-BW CT ΔΣ Modulator with 87dB DR and 91dBc IMD. 498-499 - Yun-Shiang Shu, Bang-Sup Song, Kantilal Bacrania:
A 65nm CMOS CT ΔΣ Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection. 500-501 - Lukas Dörrer, Franz Kuttner, Andreas Santner, Claus Kropf, Thomas Puaschitz, Thomas Hartig, Manfred Punzenberger:
A Continuous Time ΔΣ ADC for Voice Coding with 92dB DR in 45nm CMOS. 502-503
Non-Volatile Memory & Digital Clocking
- Yan Li, Seungpil Lee, Yupin Fong, Feng Pan, Tien-Chien Kuo, Jong Park, Tapan Samaddar, Hao Nguyen, Man Mui, Khin Htoo, Teruhiko Kamei, Masaaki Higashitani, Emilio Yero, Gyuwan Kwon, Phil Kliza, Jun Wan, Tetsuya Kaneko, Hiroshi Maejima, Hitoshi Shiga, Makoto Hamada, Norihiro Fujita, Kazunori Kanebako, Eugene Tam, Anne Koh, Iris Lu, Calvin Chia-Hong Kuo, Trung Pham, Jonathan Huynh, Qui Nguyen, Hardwell Chibvongodze, Mitsuyuki Watanabe, Ken Oowada, Grishma Shah, Byungki Woo, Ray Gao, Jim Chan, James Lan, Patrick Hong, Liping Peng, Debi Das, Dhritiman Ghosh, Vivek Kalluru, Sanjay Kulkarni, Raul Cernea, Sharon Huynh, Dimitris Pantelakis, Chi-Ming Wang, Khandker Quader:
A 16Gb 3b/ Cell NAND Flash Memory in 56nm with 8MB/s Write Rate. 506-507 - Shinji Kawai, Akira Hosogane, Shigehiro Kuge, Toshihiro Abe, Kohei Hashimoto, Tsukasa Oishi, Naoki Tsuji, Kiyohiko Sakakibara, Kenji Noguchi:
An 8kB EEPROM-Emulation DataFLASH Module for Automotive MCU. 508-509 - Ki-Tae Park, Doo-Gon Kim, Soonwook Hwang, Myounggon Kang, Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jae-hoon Jang, Hansoo Kim, Soon-Moon Jung, Yeong-Taek Lee, Changhyun Kim, Won-Seong Lee:
A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure. 510-511 - Steven C. Chan, Phillip J. Restle, Thomas J. Bucelot, Steve Weitzel, John M. Keaty, John S. Liberty, Brian K. Flachs, Richard Volant, Peter Kapusta, Jeffrey S. Zimmerman:
A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor. 512-513 - Keng-Jan Hsiao, Tai-Cheng Lee:
A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation. 514-515 - Alexander V. Rylyakov, José A. Tierno, Didem Zeliha Turker, Jean-Olivier Plouchart, Herschel A. Ainspan, Daniel J. Friedman:
A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS. 516-517 - Mamoru Sasaki:
A 9.5GHz 6ps-Skew Space-Filling-Curve Clock Distribution with 1.8V Full-Swing Standing-Wave Oscillators. 518-519
TD: Trends in Communication Circuits & Systems
- David Ruffieux, Jérémie Chabloz, Claude Müller, Franz-Xaver Pengg, Paola Tortori, Alexandre Vouilloz:
A 2.4GHz MEMS-Based Transceiver. 522-523 - Nathan Pletcher, Simone Gambini, Jan M. Rabaey:
A 2GHz 52 μW Wake-Up Receiver with -72dBm Sensitivity Using Uncertain-IF Architecture. 524-525 - Jongmin Park, Taejoong Song, Joonhoi Hur, Sang Min Lee, Jungki Choi, Kihong Kim, Jungsuk Lee, Kyutae Lim, Chang-Ho Lee, Haksun Kim, Joy Laskar:
A Fully-Integrated UHF Receiver with Multi-Resolution Spectrum-Sensing (MRSS) Functionality for IEEE 802.22 Cognitive-Radio Applications. 526-527 - Piet Wambacq, Abdelkarim Mercha, Karen Scheir, Bob Verbruggen, Jonathan Borremans, Vincent De Heyn, Steven Thijs, Dimitri Linten, Geert Van der Plas, Bertrand Parvais, Morin Dehan, Stefaan Decoutere, Charlotte Soens, Nadine Collaert, Malgorzata Jurczak:
Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies. 528-529 - Mustafa Acar, Anne-Johan Annema, Bram Nauta:
Digital Detection of Oxide Breakdown and Life-Time Extension in Submicron CMOS Technology. 530-531 - Yoshihito Hashimoto, Shuichi Nagasawa, Tetsuro Satoh, Kenji Hinode, Hideo Suzuki, Toshiyuki Miyazaki, Mutsuo Hidaka, Nobuyuki Yoshikawa, Hirotaka Terai, Akira Fujimaki:
Superconductive Single-Flux-Quantum Circuit/System Technology and 40Gb/s Switch System Demonstration. 532-533 - Tohru Kimura, Hitoshi Yano, Yuuichi Aoki, Nobuhide Yoshida, Jun Noda, Teruki Sukenari, Yusuke Konishi, Toshiyasu Nakao, Akitake Mitsuhashi, Daigo Taguchi:
A Wireless Dual-Link System for Sensor Network Applications. 534-535 - Jonathan Borremans, Piet Wambacq, Maarten Kuijk, Geert Carchon, Stefaan Decoutere:
A 400 μW 4.7-to-6.4GHz VCO under an Above-IC Inductor in 45nm CMOS. 536-537
Data-Converter Techniques
- B. Robert Gregoire, Un-Ku Moon:
An Over-60dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp with 30dB Loop Gain. 540-541 - Zhiheng Cao, Shouli Yan, Yunchu Li:
A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm CMOS. 542-543 - Peter Schvan, Jérôme Bach, Chris Falt, Philip Flemke, Robert Gibbins, Yuriy M. Greshishchev, Naim Ben-Hamida, Daniel Pollex, John Sitch, Shing-Chi Wang, John Wolczanski:
A 24GS/s 6b ADC in 90nm CMOS. 544-545 - Kang-Wei Hsueh, Yu-Kai Chou, Yu-Hsuan Tu, Yi-Fu Chen, Ya-Lun Yang, Hung-Sung Li:
A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS. 546-547 - Stephan Henzler, Siegmar Koeppe, Winfried Kamp, Hans Mulatz, Doris Schmitt-Landsiedel:
90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip Characterization. 548-549 - Bob Schell, Yannis P. Tsividis:
A Clockless ADC/DSP/DAC System with Activity-Dependent Power Dissipation and No Aliasing. 550-551 - Yasuhide Shimizu, Shigemitsu Murayama, Kohhei Kudoh, Hiroaki Yatsuda:
A Split-Load Interpolation-Amplifier-Array 300MS/s 8b Subranging ADC in 90nm CMOS. 552-553 - Denis C. Daly, Anantha P. Chandrakasan:
A 6b 0.2-to-0.9V Highly Digital Flash ADC with Comparator Redundancy. 554-555
RF & mm-Wave Power Amplifiers
- Masahiro Tanomura, Yasuhiro Hamada, Shuya Kishimoto, Masaharu Ito, Naoyuki Orihashi, Kenichi Maruhashi, Hidenori Shimawaki:
TX and RX Front-Ends for 60GHz Band in 90nm Standard Bulk CMOS. 558-559 - Debopriyo Chowdhury, Patrick Reynaert, Ali M. Niknejad:
A 60GHz 1V + 12.3dBm Transformer-Coupled Wideband PA in 90nm CMOS. 560-561 - Toshihide Suzuki, Yoichi Kawano, Masaru Sato, Tatsuya Hirose, Kazukiyo Joshin:
60 and 77GHz Power Amplifiers in Standard 90nm CMOS. 562-563 - Vincent Pinon, Frederic Hasbani, Alexandre Giry, Denis Pache, Christophe Garnier:
A Single-Chip WCDMA Envelope Reconstruction LDMOS PA with 130MHz Switched-Mode Power Supply. 564-565 - Jeffrey S. Walling, Hasnain Lakdawala, Yorgos Palaskas, Ashoke Ravi, Ofir Degani, Krishnamurthy Soumyanath, David J. Allstot:
A 28.6dBm 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation. 566-567 - Shervin Moloudi, Koji Takinami, Michael Youssef, Mohyee Mikhemar, Asad A. Abidi:
An Outphasing Power Amplifier for a Software-Defined Radio Transmitter. 568-569 - Ichiro Aoki, Scott D. Kee, Rahul Magoon, Roberto Aparicio, Florian Bohn, Jeff Zachan, Geoff Hatcher, Donald McClymont, Ali Hajimiri:
A Fully Integrated Quad-Band GSM/GPRS CMOS Power Amplifier. 570-571 - Antonino Scuderi, Carmelo Santagati, Michele Vaiana, Francesco Pidalà, Mario Paparo:
Balanced SiGe PA Module for Multi-Band and Multi-Mode Cellular-Phone Applications. 572-573
MEMS & Sensors
- Caspar P. L. van Vroonhoven, Kofi A. A. Makinwa:
A CMOS Temperature-to-Digital Converter with an Inaccuracy of ± 0.5° C (3σ)from -55 to 125°C. 576-577 - Mika Kämäräinen, Matti Paavola, Mikko Saukoski, Erkka Laulainen, Lauri Koskinen, Marko Kosunen, Kari Halonen:
A 1.5μW 1V 2nd-Order ΔΣ Sensor Front-End with Signal Boosting and Offset Compensation for a Capacitive 3-Axis Micro-Accelerometer. 578-579 - Chinwuba D. Ezekwe, Bernhard E. Boser:
A Mode-Matching ΔΣ Closed-Loop Vibratory-Gyroscope Readout Interface with a 0.004°/s/√Hz Noise Floor over a 50Hz Band. 580-581 - Tamio Ikehashi, Takayuki Miyazaki, Hiroaki Yamazaki, Atsushi Suzuki, Etsuji Ogawa, Shinji Miyano, Tomohiro Saito, Tatsuya Ohguro, Takeshi Miyagi, Yoshiaki Sugizaki, Nobuaki Otsuka, Hideki Shibata, Yoshiaki Toyoshima:
An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation. 582-583 - Dongning Zhao, Faisal Zaman, Farrokh Ayazi:
A Chopper-Stabilized Lateral-BJT-Input Interface in 0.6μm CMOS for Capacitive Accelerometers. 584-585 - Leslie Landsberger, Oleg Grudin, Gennadiy Frolov, Zhengrong Huang, Saed Salman, Tommy Tsang, Mathieu Renaud, Bowei Zhang:
Single-Chip CMOS Analog Sensor-Conditioning ICs with Integrated Electrically-Adjustable Passive Resistors. 586-587 - Nicola Massari, Massimo Gottardi, Syed A. Jawed:
A 100μW 64×128-Pixel Contrast-Based Asynchronous Binary Vision Sensor for Wireless Sensor Networks. 588-589 - Mark J. Milgrew, Mathis O. Riehle, David R. S. Cumming:
A 16×16 CMOS Proton Camera Array for Direct Extracellular Imaging of Hydrogen-Ion Activity. 590-591
Short Course
- Ian Galton, Jonathan Audy, Vadim Ivanov, Stefan Rusu, Seth R. Sanders:
Short Course. 648-649
Forums
- Kevin Zhang:
Embedded Memory Design for Nano-Scale VLSI Systems (Forum). 650-651 - Albert Theuwissen:
Wide Dynamic Range Imaging (Forum). 652-653 - Stefan Heinen, Francesco Svelto, Jan Craninckx, Mototsugu Hamada, Domine Leenaerts, Chris Rudell:
Architectures and Circuit Techniques for Nanoscale RF CMOS (Forum). 654-655 - Eugenio Cantatore, Siva G. Narendra:
Power Systems from the Gigawatt to the Microwatt - Generation, Distribution, Storage and Efficient Use of Energy (Forum). 656-657 - Robert Payne:
Future of High-Speed Transceivers (Forum). 658-659 - Ron Ho:
Transistor Variability in Nanometer-Scale Technologies (Forum). 660-661 - Andrea Baschirotto:
Digitally-Assisted RF Circuits (Forum). 662-663
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-08 20:17 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
