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Functional approaches to generating orderings for efficient symbolic representations

Published: 01 July 1992 Publication History
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References

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C.L. Berman, "Circuit width, register allocation, and reduced function graphs," IBM Res. Rep. RC 14127, Nov. 1988.
[2]
C.L. Berman, "Ordered Binary Decision Diagrams and Circuit Structure," Extended Abstract, Proc. international Conference Computer Design, Oct. 1989, pp. 392-395.
[3]
K.S. Brace, R.E. Bryant and R.L. Rudell, "Efficient implementation of a BDD package," Proc. A CM/IEEE PTth Design Automation Conf., Jun. 1990, pp. 40-45.
[4]
F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Jun. 1985, pp. 695-698.
[5]
R.E. Bryant, "Graph-based algorithms for Boolean function manipulation," IEEE Transactions on Computers, Vol C-35, No. 8, Aug. 1986, pp. 677-692.
[6]
R.E. Bryant, "On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication," IEEE Transactions on Computers, Vol. C-40, No. 2, Feb. 1991, pp. 205-213.
[7]
K.M. Butler, D.E. Ross, R. Kaput and M.R. Mercer, "Heuristics to compute variable orderings for efficient manipulation of ordered binary decision diagrams," Proc. ACM-IEEE P8th Design Automation Conference, Jun. 1991, pp. 417-420.
[8]
S.J. Friedman and K.J. Supowit, "Finding the optimal variable ordering for binary decision diagrams," IEEE Trans. on Comput., vol C-39, no. 5, May 1990, pp. 710-713. see also Proc. A CM. IEEE 24th Design Automation Conference, Jun. 1987, pp. 348-356.
[9]
M. Fujita, H. Fujisawa and N. Kawato, "Evaluation and improvements of Boolean comparison method based on binary decision diagrams," Dig. Technical Papers, International Conference on CAD, Nov. 1988, pp. 2-5.
[10]
M. Fujita, Y. Matunaga and T. Kakuda, "On the variable ordering for binary decision diagrams for the application of multilevel logic synthesis," Proceedings of the European Design Automation Conference, Feb. 1991, pp. 50-54.
[11]
N. Ishiura, H. Sawada and S. Yajima, "Minimization of binary decision diagrams based on exchange of variables," Proc. International Conference of Computer-Aided Design, Nov. 1991, pp. 472-475.
[12]
S. Malik, A.R. Wang, R.K. Brayton and A. Sangiovanni-Vincentelli, "Logic verification using binary decision diagrams in a logic synthesis environment," Dig. Technical Papers, International Conference on CAD, Nov. 1988, pp. 6-9.
[13]
S. Minato, N. Ishiura and S. Yajima, "Shared Binary Decision Diagram with attributed edges for efficient Boolean function manipulation," Proc. 27th A CM/IEEE Deszgn Automation Conference, Jun. 1990, pp. 52-57.
[14]
D.E. Ross, "Functional calculations using ordered partial multi decision diagrams," Ph.D. Dissertation, The University of Texas at Austin, Aug. 1990.
[15]
D.E. Ross, K.M. Butler, R. Kapur and M.R. Mercer, "Fast Functional Evaluation of Candidate OBDD Variable Orderings," Proceedings of the European Design Automation Conference, Feb. 1991, pp. 4-10.

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cover image ACM Conferences
DAC '92: Proceedings of the 29th ACM/IEEE Design Automation Conference
July 1992
752 pages
ISBN:089791516X

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Published: 01 July 1992

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DAC92: The 29th ACM/IEEE-CS Design Automation Conference
June 8 - 12, 1992
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