A 1.2v 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOs
Pages 187 - 192
Abstract
This paper reports design, optimization, efficiency and measurement results of the 12 bits dual-residue multi-step A/D converter. The calibration procedure based on the steepest-descent estimation method is enhanced with dedicated embedded sensors, which register on-chip process parameter and temperature variations. The prototype A/D converter with performance of 68.6 dB SNDR, 70.3 dB SNR, 78.1 dB SFDR, 11.1 ENOB at 60 MS/s has been fabricated in standard single poly, six metal 90 nm CMOS, consumes only 55 mW and measures 0.75 mm2. The on-chip calibration logic occupies an area of 0.14 mm2 and consumes 11 mW of power.
References
[1]
V. Petrescu, M. Pelgrom, H. Veendrick, P. Pavithran, J. Wieling, "Monitors for a Signal Integrity Measurement System", Proceedings of IEEE European Solid-State Circuit Conference, pp. 122--125, 2006
[2]
J. Yuan, N.H. Farhat, J. van der Spiegel, "Background Calibration With Piecewise Linearized Error Model for CMOS Pipeline A/D Converter", IEEE Transactions on Circuits and Systems-I, vol. 55, no. 1, pp. 311--321, 2008
[3]
H. Wang, X. Wang, P.J. Hurst, S.H.Lewis, "Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA", IEEE Journal of Solid-State Circuits, vol. 44, no. 10, pp. 2780--2789, 2008
[4]
Y.-J. Kim, H.-C. Choi, G.-C. Ahn, S.H. Lee, "A 12 bit 50 MS/s CMOS Nyquist A/D converter With a Fully Differential Class-AB Switched Op-Amp", IEEE Journal of Solid-State Circuits, vol. 45, no. 3, pp. 620--628, 2010
[5]
H.-C. Choi, Y.-J. Kim, G.-C. Ahn, S.-H. Lee, "A 1.2-V 12-b 120MS/S SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration", IEEE Transactions on Circuits and Systems-I, vol. 56, no. 5, pp. 894--901, 2009
[6]
A. Panigada, I. Galton, "A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distoriton Correction", IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3314--3328, 2009
[7]
B.D. Sahoo, B. Razavi, "A 12-Bit 200-MHz CMOS ADC", IEEE Journal of Solid-State Circuits, vol. 44, no. 9, pp. 2366--2380, 2009
[8]
J. Tsimbinos, K.V. Lever, "Improved Error-Table Compensation of A/D Converters", IEE Proceedings - Circuits, Devices and Systems, vol. 144, no. 6, pp. 343--349, 1997
[9]
P. Händel, M. Skoglund, M. Pettersson, "A Calibration Scheme for Imperfect Quantizers", IEEE Transactions on Instrumentation and Measurement, vol. 49, no. 11, pp. 1063--1068, 2000
[10]
P. Arpaia, P. Daponte, L. Michaeli, "Influence of the architecture on ADC error modelling", IEEE Transactions on Instrumentation and Measurement, vol. 48, pp. 956--966, 1999
[11]
K. Noguchi, T. Hashida, M. Nagata, "On-Chip Analog Circuit Diagnosis in Systems-on-Chip Integration", Proceedings of IEEE European Solid-State Circuit Conference, pp. 118--121, 2006
[12]
A. Charoenrook, M. Soma, "A Fault Diagnosis Technique for Flash ADC's", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 43, pp. 445--457, 1996
[13]
F.H. Irons, D.M. Hummels, I.N. Papantonopoulos, C.A. Zoldi, "Analog-to-Digital Converter Error Diagnosis", Proceedings of IEEE Instrumentation and Measurement Technology Conference, pp. 732--737, 1996
[14]
A. Zjajo, J. Pineda de Gyvez, "DfT for Full Accessibility of Multi-Stpe Analog to Digital Converters", Proceedings of IEEE International Symposium on VLSI Design, Automation and Test, pp. 73--76, 2008
[15]
D. Schinkel, R.P. de Boer, A.J. Annema, A.J.M. van Tuijl, "A 1-V 15µW High-Precision Temperature Switch", Proceedings of IEEE European Solid-State Conference, pp. 77--80, 2001
[16]
W.C. Black Jr., D.A. Hodges, "Time Interleaved Converter Arrays," IEEE Journal of Solid-State Circuits, vol.15, no.6, pp. 1022--1029, 1980
[17]
K. Poulton, R. Neff, A. Muto, W. Liu, A. Burnstein, M. Heshami, "A 4GSample/s 8b ADC in 0.35μm CMOS", IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 166--167, 2002
[18]
M. Louwsma, E.J.M. van Tuijl, M. Vertregt, B. Nauta, "A 1.35 GS/s, 10b, 175mW Time-Interleaved AD Converter in 0.13 μm CMOS", Proceedings of IEEE Symposium on VLSI Circuits, pp. 62--63, 2007
[19]
K. Nagaraj, D.A. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio, T.R. Viswanathan, "A Dual-Mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D Converter in a 0.25-μm Digital CMOS Process," IEEE Journal of Solid-State Circuits, vol. 35, no. 12, pp. 1760--1768, 2000
[20]
L. Sumanen, M. Waltari, K.A.I. Halonen, "A 10-bit 200-MS/s CMOS Parallel Pipeline A/D converter", Proceedings of IEEE European Solid-State Circuits Conference, pp. 439--442, 2000
[21]
A.N. Karanicolas, H.-S. Lee, K.L. Bacrania, "A 15-b 1-Msample/s Digitally Self-Calibrated Pipeline ADC", IEEE Journal of Solid-State Circuits, vol. 28, no. 12, pp. 1207--1215, 1993
[22]
A. Yukawa, "An 8-bit High-Speed CMOS A/D Converter," IEEE Journal of Solid-State Circuits, vol. 20, no. 3, pp. 775--779, 1985
[23]
S.H. Lewis, H.S. Fetterman, G.F. Gross, R. Ramachandran, T.R. Viswanathan, "A 10-b 20-Msample/s Analog-to-Digital Converter", IEEE Journal of Solid-State Circuits, vol. 27, no. 3, pp. 351--358, 1992
[24]
G.M. Yin, F. op't Eynde, W. Sansen, "A High-Speed CMOS Comparator with 8-b Resolution", IEEE Journal of Solid-State Circuits, vol. 27, no. 2, pp. 208--211, 1992
[25]
B. Nauta, A.G.W. Venes, "A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter", IEEE Journal of Solid-State Circuits, vol. 30, no. 12, pp. 1302--1308, 1995
[26]
P. Vorenkamp, R. Roovers, "A 12-bit, 60-MSample/s Cascaded Folding and Interpolating ADC", IEEE Journal of Solid-State Circuits, vol. 32, no. 12, pp. 1876--1886, 1997
[27]
C. Mangelsdorf, H. Malik, S.-H. Lee, S Hisano, M. Martin, "A Two Residue Architecture for Mulitstage ADCs", IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 64--65, 1993
[28]
J.E. Dennis, R.B. Schnabel, Numerical Methods for Unconstrained Optimization and Nonlinear Equations, Prentice-Hall, 1983
[29]
B. Widrow, S.D. Stearns, Adaptive Signal Processing, Prentice-Hall, 1985
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Published In
August 2011
434 pages
ISBN:9781612846606
- General Chairs:
- Naehyuck Chang,
- Hiroshi Nakamura,
- Koji Inoue,
- Program Chairs:
- Kenichi Osada,
- Massimo Poncino
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IEEE Press
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Published: 01 August 2011
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Qualifiers
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ISLPED'11
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ISLPED'11: International Symposium on Low Power Electronics and Design
August 1 - 3, 2011
Fukuoka, Japan
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