Article

System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip

Authors:

Vittorio Zaccaria,

Roberto ZafalonAuthors Info & Claims

DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 3

Page 30318

Published: 16 February 2004 Publication History

Abstract

Today's System on Chip (SoC) technology can achieve unprecedented computing speed that is shifting the IC design bottleneck from computation capacity to communication bandwidth and flexibility. This paper presents an innovative methodology for automatically generating the energy models of a versatile and parametric on-chip communication IP (STBus). Eventually, those models are linked to a standard SystemC simulator, running at BCA and TLM abstractionlevel. To make the system power simulation fast and effective, we enhanced the STBus class library with a new set of power profiling features ("Power API"), allowing to perform power analysis either statically (i.e.: total avg. power) or at simulation runtime (i.e.: dynamic profiling). In addition to random patterns, our methodology has been extensively benchmarked with the high-level SystemC simulation of a real world multi-processor platform (MP-ARM). It consists of four ARM7TDMI processors accessing a number of peripheral targets (including several banks of SRAMs, Interrupt's slaves and ROMs) through the STBus communication infrastructure. A remarkable amount of SW layers are executed on top of MP-ARM platform, including a distributed real-time operating system (RTEMS) and a set of multi-tasking DSP applications. The power analysis of the benchmark platform proves to be effective and highly correlated, with an average error of 9% and a RMS of 0.015 mW vs. the reference (i.e. gate level) power figures.

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Cited By

Oveis-Gharan MKhan GBarros FPerumalla KEwald R(2014)Power and chip-area aware network-on-chip modeling for system on chip simulationProceedings of the 7th International ICST Conference on Simulation Tools and Techniques10.4108/icst.simutools.2014.254626(178-185)Online publication date: 17-Mar-2014
https://dl.acm.org/doi/10.4108/icst.simutools.2014.254626
Hsu CLiao JFang SWeng CHuang SHsieh WYeh JStok LDutt NHassoun S(2011)PowerDepotProceedings of the 48th Design Automation Conference10.1145/2024724.2024736(47-52)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024736
Kahng ALin BSamadi KLin Y(2010)Improved on-chip router analytical power and area modelingProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899773(241-246)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899773
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Index Terms

System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip
1. Hardware

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Published In

cover image ACM Conferences

DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 3

February 2004

326 pages

ISBN:0769520855

Copyright © Copyright (c) 2004 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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SIGDA: ACM Special Interest Group on Design Automation

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IEEE Computer Society

United States

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Published: 16 February 2004

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DATE04: Design, Automation and Test in Europe 2004

February 16 - 20, 2004

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Oveis-Gharan MKhan GBarros FPerumalla KEwald R(2014)Power and chip-area aware network-on-chip modeling for system on chip simulationProceedings of the 7th International ICST Conference on Simulation Tools and Techniques10.4108/icst.simutools.2014.254626(178-185)Online publication date: 17-Mar-2014
https://dl.acm.org/doi/10.4108/icst.simutools.2014.254626
Hsu CLiao JFang SWeng CHuang SHsieh WYeh JStok LDutt NHassoun S(2011)PowerDepotProceedings of the 48th Design Automation Conference10.1145/2024724.2024736(47-52)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024736
Kahng ALin BSamadi KLin Y(2010)Improved on-chip router analytical power and area modelingProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899773(241-246)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899773
Pasricha SPark YKurdahi FDutt N(2010)CAPPSIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200930418:2(209-221)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2009304
Kahng ALi BPeh LSamadi KBenini LDe Micheli GAl-Hashimi BMueller W(2009)ORION 2.0Proceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874721(423-428)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874721
Pasricha SPark YDutt NKurdahi F(2009)System-level PVT variation-aware power exploration of on-chip communication architecturesACM Transactions on Design Automation of Electronic Systems10.1145/1497561.149756314:2(1-25)Online publication date: 7-Apr-2009
https://dl.acm.org/doi/10.1145/1497561.1497563
Elmiligi HMorgan AEl-Kharashi MGebali F(2009)Power optimization for application-specific networks-on-chipsMicroprocessors & Microsystems10.1016/j.micpro.2009.03.00233:5-6(343-355)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1016/j.micpro.2009.03.002
Lee SBagherzadeh N(2009)A high level power model for Network-on-Chip (NoC) routerComputers and Electrical Engineering10.1016/j.compeleceng.2008.11.02335:6(837-845)Online publication date: 1-Nov-2009
https://dl.acm.org/doi/10.1016/j.compeleceng.2008.11.023
Varma ADebes EKozintsev IKlein PJacob B(2008)Accurate and fast system-level power modelingACM Transactions on Embedded Computing Systems10.1145/1347375.13473787:3(1-20)Online publication date: 8-May-2008
https://dl.acm.org/doi/10.1145/1347375.1347378
Khatib IPoletti FBertozzi DBenini LBechara MKhalifeh HJantsch ANabiev R(2008)A multiprocessor system-on-chip for real-time biomedical monitoring and analysisACM Transactions on Design Automation of Electronic Systems10.1145/1344418.134442713:2(1-21)Online publication date: 23-Apr-2008
https://dl.acm.org/doi/10.1145/1344418.1344427
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