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Performance of interconnection rip-up and reroute strategies

Authors:

William A. Dees, Jr.,

Robert J. Smith, IIAuthors Info & Claims

DAC '81: Proceedings of the 18th Design Automation Conference

Pages 382 - 390

Published: 29 June 1981 Publication History

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Abstract

Rip-up and reroute strategies can be applied following use of conventional wiring algorithms to calculate paths for residual connections failed by preceding techniques. The removal of blocking wire to allow new path runs inevitably introduces new (reroute) wiring requirements. In this paper we address the performance implications of various rates of success experienced while attempting reroutes. Using statistical approaches, we develop formulas which allow calculation of expected completion rate and computational effort for several types of rip-up and reroute algorithms. It is found that a basic router having modest completion rate behavior can be used to achieve surprisingly high completion rates, with rip-up strategies.

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Dees, W. A., Jr., "Connectivity Optimization Utilizing Shove Aside and Rip-up Techniques", Master's Thesis, University of Texas at Austin, May, 1981.

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Cited By

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Khasawneh MMadden PHomayoun HTaskin BMohsenin TZhao W(2019)HydraRouteProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3317997(177-182)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3317997
Xu XYu BGao JHsu CPan D(2016)PARRACM Transactions on Design Automation of Electronic Systems10.1145/284261221:3(1-21)Online publication date: 16-May-2016
https://dl.acm.org/doi/10.1145/2842612
Ziesemer AReis R(2015)Physical design automation of transistor networksMicroelectronic Engineering10.1016/j.mee.2015.10.018148:C(122-128)Online publication date: 1-Dec-2015
https://dl.acm.org/doi/10.1016/j.mee.2015.10.018
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Index Terms

Performance of interconnection rip-up and reroute strategies
1. Hardware
  1. Integrated circuits
    1. Interconnect
  2. Robustness
2. Theory of computation
  1. Design and analysis of algorithms
    1. Approximation algorithms analysis
      1. Routing and network design problems

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DAC '81: Proceedings of the 18th Design Automation Conference

June 1981

899 pages

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IEEE Press

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Published: 29 June 1981

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Khasawneh MMadden PHomayoun HTaskin BMohsenin TZhao W(2019)HydraRouteProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3317997(177-182)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3317997
Xu XYu BGao JHsu CPan D(2016)PARRACM Transactions on Design Automation of Electronic Systems10.1145/284261221:3(1-21)Online publication date: 16-May-2016
https://dl.acm.org/doi/10.1145/2842612
Ziesemer AReis R(2015)Physical design automation of transistor networksMicroelectronic Engineering10.1016/j.mee.2015.10.018148:C(122-128)Online publication date: 1-Dec-2015
https://dl.acm.org/doi/10.1016/j.mee.2015.10.018
Rakai LBehjat LAreibi STerlaky T(2009)A multilevel congestion-based global routerVLSI Design10.1155/2009/5373412009(1-1)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1155/2009/537341
Li-Guo SYu-Xian J(2006)A route system based on ant colony for coarse-grain reconfigurable architectureProceedings of the Second international conference on Advances in Natural Computation - Volume Part II10.1007/11881223_27(215-221)Online publication date: 24-Sep-2006
https://dl.acm.org/doi/10.1007/11881223_27
Magen NKolodny AWeiser UShamir NScheffer LMarkov I(2004)Interconnect-power dissipation in a microprocessorProceedings of the 2004 international workshop on System level interconnect prediction10.1145/966747.966750(7-13)Online publication date: 14-Feb-2004
https://dl.acm.org/doi/10.1145/966747.966750
Chowdhury AFrieder OWan P(2002)On the Design, Development, Deployment, and Network Survivability Analysis of the Dynamic Routing System ProtocolThe Journal of Supercomputing10.1023/A:101410432683921:3(239-256)Online publication date: 1-Mar-2002
https://dl.acm.org/doi/10.1023/A%3A1014104326839
Lakamraju VTessier RTrimberger SHauck S(2000)Tolerating operational faults in cluster-based FPGAsProceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays10.1145/329166.329205(187-194)Online publication date: 1-Feb-2000
https://dl.acm.org/doi/10.1145/329166.329205
McMurchie LEbeling CChan PRose J(1995)PathFinderProceedings of the 1995 ACM third international symposium on Field-programmable gate arrays10.1145/201310.201328(111-117)Online publication date: 15-Feb-1995
https://dl.acm.org/doi/10.1145/201310.201328
Tong CWu C(1995)Routing in a Three-Dimensional ChipIEEE Transactions on Computers10.1109/12.36800644:1(106-117)Online publication date: 1-Jan-1995
https://dl.acm.org/doi/10.1109/12.368006
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Automated rip-up and reroute techniques

SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal

V-GR: 3D Global Routing with via Minimization and Multi-Strategy Rip-Up and Rerouting

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Recommendations

Automated rip-up and reroute techniques

SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal

V-GR: 3D Global Routing with via Minimization and Multi-Strategy Rip-Up and Rerouting

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