Five placement procedures which combine three basic algorithms are developed and incorporated to our system. Evaluation of results is presented. Compared with manual design the optimum procedure reduces block size by 6.5%. The normalized area for one transistor (NA) is defined as the measure of automatic layout performance. NA is the product of wiring pitch. Optimum NA is confirmed to be 14.9 for manual design and 13.9 for automatic layout using the optimum procedure.

This system is applicable to both custom logic LSIs and masterslice LSIs and has been applied to layouts of many such devices.

References

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H. Terai, et al.; Automatic Placement and Routing Program for Logic VLSI Design based on Hierarchical Layout Method, Proc. of Conf. ICCC ('82.9).

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Y. Ohno, et al.; Integrated Design Automation System for Custom and Gate Array VLSI Design, Proc. of Conf. ICCC ('82.9).

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T. Adachi, et al.; Hierarchical Top-down Layout Method for VLSI Chip, Proc. of 19th DA Conf. ('82.6).

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M.Hanan, et al.; "Placement Techniques", Chap.5 in Design Automation of Digital Systems, Vol. 1, Prentice-Hall ('72), pp.213-282.

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T.Kozawa, et al.; Block and Track Method for Automated Layout Generation of MOS-LSI Arrays, Digt. of ISSCC72, p62 ('72.2).

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D. M. Schuler, et al.; Clustering and Linear Placement, Proc. of 9th DA Workshop ('72.6).

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T. Kozawa, et al.; Advanced LILAC-an Automated Layout Generation System for MOS/LSIs, Proc. of 11th DA Workshop ('74.6).

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Cited By

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Srinivasan SKamakoti VBhattacharya A(2013)A Novel Algorithm for Fast Synthesis of DNA Probes on MicroarraysACM Journal on Emerging Technologies in Computing Systems10.1145/2422094.24220959:1(1-17)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1145/2422094.2422095
Kahng AMandoiu IReda SXu XZelikovsky A(2003)Evaluation of Placement Techniques for DNA Probe Array LayoutProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009901Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009901
Ogawa YTerai HKozawa TShaklee DNewton A(1988)Automatic layout procedures for serial routing devicesProceedings of the 25th ACM/IEEE Design Automation Conference10.5555/285730.285838(642-645)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.5555/285730.285838
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Index Terms

Automatic placement algorithms for high packing density V L S I
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

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DAC '83: Proceedings of the 20th Design Automation Conference

June 1983

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Published: 27 June 1983

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Srinivasan SKamakoti VBhattacharya A(2013)A Novel Algorithm for Fast Synthesis of DNA Probes on MicroarraysACM Journal on Emerging Technologies in Computing Systems10.1145/2422094.24220959:1(1-17)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1145/2422094.2422095
Kahng AMandoiu IReda SXu XZelikovsky A(2003)Evaluation of Placement Techniques for DNA Probe Array LayoutProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009901Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009901
Ogawa YTerai HKozawa TShaklee DNewton A(1988)Automatic layout procedures for serial routing devicesProceedings of the 25th ACM/IEEE Design Automation Conference10.5555/285730.285838(642-645)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.5555/285730.285838
Mallela SGrover LShaklee DNewton A(1988)Clustering based simulated annealing for standard cell placementProceedings of the 25th ACM/IEEE Design Automation Conference10.5555/285730.285781(312-317)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.5555/285730.285781
Preas BKarger PThomas D(1986)Automatic placement a review of current techniques (tutorial session)Proceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318124(622-629)Online publication date: 2-Jul-1986
https://dl.acm.org/doi/10.5555/318013.318124
Ogawa YIshii TShiraishi YTerai HKozawa TYuyama KChiba KThomas D(1986)Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIsProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318079(404-410)Online publication date: 2-Jul-1986
https://dl.acm.org/doi/10.5555/318013.318079
Terai HHayase MKozawa TOfek HO'Neill L(1985)A routing procedure for mixed array of custom macros and standard cellsProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317936(503-508)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.317936
Spira PHage COfek HO'Neill L(1985)Hardware acceleration of gate array layoutProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317913(359-366)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.317913
Kozawa TMiura CTerai HLambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)Combine and top down block placement algorithm for hierarchical logic VLSI layoutProceedings of the 21st Design Automation Conference10.5555/800033.800876(667-669)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800876

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Constraint-driven large-scale circuit placement algorithms

Cell density-driven detailed placement with displacement constraint

Density-aware Detailed Placement with Instant Legalization

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Constraint-driven large-scale circuit placement algorithms

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Density-aware Detailed Placement with Instant Legalization

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