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An efficient algorithm to integrated scheduling and allocation in high-level test synthesis

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Z. PengAuthors Info & Claims

DATE '98: Proceedings of the conference on Design, automation and test in Europe

Pages 74 - 81

Published: 23 February 1998 Publication History

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Abstract

This paper presents a high-level test synthesis algorithm for operation scheduling and data path allocation. Contrary to other works in which scheduling and allocation are performed independently, our approach integrates these two tasks by performing them simultaneously so that the effects of scheduling and allocation on testability are exploited more effectively. The approach is based on an algorithm which applies a sequence of semantics-preserving transformations to a design to generate an efficient RT level implementation from a VHDL behavioral specification. Experimental results show the advantages of the proposed algorithm.

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Cited By

Ravi SJoseph M(2014)High-Level Test SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/262775419:4(1-27)Online publication date: 29-Aug-2014
https://dl.acm.org/doi/10.1145/2627754
Wang SYeh T(2009)High-level test synthesis with hierarchical test generation for delay-fault testabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.202636028:10(1583-1596)Online publication date: 1-Oct-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2026360
Wang SYeh TLauwereins RMadsen J(2007)High-level test synthesis for delay fault testabilityProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266378(45-50)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266378
Show More Cited By

Index Terms

An efficient algorithm to integrated scheduling and allocation in high-level test synthesis
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
      1. Datapath optimization
  2. Robustness
2. Theory of computation
  1. Design and analysis of algorithms
    1. Approximation algorithms analysis
      1. Scheduling algorithms
    2. Online algorithms
      1. Online learning algorithms
        Scheduling algorithms
  2. Theory and algorithms for application domains
    1. Machine learning theory
      1. Reinforcement learning
        Sequential decision making

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Published In

cover image ACM Conferences

DATE '98: Proceedings of the conference on Design, automation and test in Europe

February 1998

940 pages

ISBN:0818683597

Copyright © Copyright © 1998 IEEE. All Rights Reserved.

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SIGDA: ACM Special Interest Group on Design Automation

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IEEE Computer Society

United States

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Published: 23 February 1998

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DATE98

Sponsor:

SIGDA

DATE98: Design, Automation & Test in Europe

February 23 - 26, 1998

Le Palais des Congrés de Paris, France

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Ravi SJoseph M(2014)High-Level Test SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/262775419:4(1-27)Online publication date: 29-Aug-2014
https://dl.acm.org/doi/10.1145/2627754
Wang SYeh T(2009)High-level test synthesis with hierarchical test generation for delay-fault testabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.202636028:10(1583-1596)Online publication date: 1-Oct-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2026360
Wang SYeh TLauwereins RMadsen J(2007)High-level test synthesis for delay fault testabilityProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266378(45-50)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266378
Aminzadeh SSafari SZhou HMacii EYan ZMassoud Y(2007)Co-evolutionary high-level test synthesisProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228805(67-72)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228805
Yang TPeng Z(1999)Incremental Testability Analysis for Partial Scan Selection and Design TransformationsJournal of Electronic Testing: Theory and Applications10.1023/A:100835752421414:1-2(103-113)Online publication date: 1-Feb-1999
https://dl.acm.org/doi/10.1023/A%3A1008357524214

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