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What is the cost of delay insensitivity?

Published: 07 November 1999 Publication History

Abstract

Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous speed-independent (SI) circuits, whose behaviour is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical. The paper presents an approach for automated synthesis of globally DI and locally SI circuits. It is based on order relaxation, a simple graphical transformation of a circuit's behavioural specification, for which Signal Transition Graph, an interpreted Petri net, is used. The method is successfully tested on a set of benchmarks and a realistic design example. It proves effective showing average cost of DI interfacing at about 40% for area and 20% for speed.

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cover image ACM Conferences
ICCAD '99: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
November 1999
613 pages
ISBN:0780358325

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IEEE Press

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Published: 07 November 1999

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ICCAD '99
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ICCAD '99: The International Conference on Computer Aided Design.
November 7 - 11, 1999
California, San Jose, USA

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