Process variation aware data management for magnetic skyrmions racetrack memory
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Process variation aware data management for magnetic skyrmions racetrack memory
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)Skyrmions racetrack memory (SKM) has been identified as a promising candidate for future on-chip cache. Similar to many other nanoscale technologies, process variations also adversely impact the reliability and performance of SKM cache. In this work, we ...
Working with process variation aware caches
DATE '07: Proceedings of the conference on Design, automation and test in EuropeDeep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware components. This is severe in the case of memory components as minimum sized ...
Process variation aware data management for STT-RAM cache design
ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and designThe spin-transfer torque random access memory (STT-RAM) has gained increasing attentions for its high density, fast read access, zero standby power, and good scalability. The recently proposed retention-relax design further improves STT-RAM write access ...
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- IEEE Circuits and Systems Society
- SIGDA: ACM Special Interest Group on Design Automation
- IEEE Council on Electronic Design Automation (CEDA)
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