Multi-Path Scheduling for Multimedia Traffic in Safety Critical On-chip Network
Pages 37 - 46
Abstract
Networks-on-Chip (NoCs) for contemporary multiprocessors systems must integrate complex multimedia applications which require not only high performance but also timing guarantees. However, in existing NoCs, designed for real-time systems, timing constraints are frequently implemented at the cost of decreased hardware utilization, i.e strict spatial or temporal isolation between transmissions. In this work, we propose an alternative - multi-path scheduling (MPS) - mechanism exploiting the multidimensional structure of NoCs, to combine the path selection and the temporal flow control based on the global state of the system. Consequently, MPS allows a safe sharing of NoC resources while preserving a high utilization achieved through a predictable load distribution of data traffic among different paths, reachable from source to destination. We demonstrate using benchmarks, that MPS not only provides higher average performance compared to existing solutions, but also allows to provide worst-case guarantees. We prove this important feature using formal timing analysis. Moreover, MPS induces a low implementation overhead as it can be applied to many existing wormhole-switched and performance optimized NoCs without requiring complex hardware modifications.
References
[1]
F. Dobrian, V. Sekar, A. Awan, I. Stoica, D. Joseph, A. Ganjam, J. Zhan, and H. Zhang, "Understanding the impact of video quality on user engagement," SIGCOMM Comput. Commun. Rev., 2011.
[2]
K. Goossens and A. Hansson, "The aethereal network on chip after ten years: Goals, evolution, lessons, and future," in DAC, 2010.
[3]
K. Goossens, J. Dielissen, and A. Radulescu, "Æthereal network on chip: concepts, architectures, and implementations," Design & Test of Computers, IEEE, vol. 22, no. 5, pp. 414--421, 2005.
[4]
H. Zhang, "Service disciplines for guaranteed performance service in packet-switching networks," in Proc. of the IEEE, 1995.
[5]
A. Kostrzewa, S. Saidi, and R. Ernst, "Dynamic control for mixed-critical networks-on-chip," in Real-Time Systems Symposium, 2015 IEEE, pp. 317--326, Dec 2015.
[6]
A. Kostrzewa, S. Saidi, L. Ecco, and R. Ernst, "Dynamic admission control for real-time networks-on-chips," in ASP-DAC, 2016.
[7]
U. Y. Ogras, J. Hu, and R. Marculescu, "Key research problems in noc design: A holistic perspective," in CODES+ISSS, 2005.
[8]
W. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., 2003.
[9]
H. Wassel et al., "Surfnoc: A low latency and provably non-interfering approach to secure networks-on-chip," 2013.
[10]
A. Psarras, I. Seitanidis, C. Nicopoulos, and G. Dimitrakopoulos, "Phasenoc: Tdm scheduling at the virtual-channel level for efficient network traffic isolation," in DATE, 2015.
[11]
J. Diemer and et al., "Real-time communication analysis for networks with two-stage arbitration," in EMSOFT, (New York, NY, USA), pp. 243--252, ACM, 2011.
[12]
E. Bolotin and et al., "Qnoc: Qos architecture and design process for network on chip," JOURNAL OF SYSTEMS ARCHITECTURE, 2004.
[13]
Z. Shi and A. Burns, "Real-time communication analysis for on-chip networks with wormhole switching," in NoCS 2008, 2008.
[14]
J. Hu and R. Marculescu, "Dyad: Smart routing for networks-on-chip," in Proceedings of the 41st Annual Design Automation Conference, DAC '04, (New York, NY, USA), pp. 260--263, ACM, 2004.
[15]
W. Dally and H. Aoki, "Deadlock-free adaptive routing in multicomputer networks using virtual channels," Parallel and Distributed Systems, IEEE Transactions on, vol. 4, pp. 466--475, Apr 1993.
[16]
D. Fick, A. DeOrio, G. Chen, V. Bertacco, D. Sylvester, and D. Blaauw, "A highly resilient routing algorithm for fault-tolerant nocs," in Proceedings of the Conference on Design, Automation and Test in Europe, DATE '09, (3001 Leuven, Belgium, Belgium), pp. 21--26, European Design and Automation Association, 2009.
[17]
G. Ascia, V. Catania, M. Palesi, and D. Patti, "Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip," IEEE Transactions on Computers, vol. 57, pp. 809--820, June 2008.
[18]
R. Marculescu, U. Y. Ogras, L. S. Peh, N. E. Jerger, and Y. Hoskote, "Outstanding research problems in noc design: System, microarchitecture, and circuit perspectives," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, pp. 3--21, Jan 2009.
[19]
H. Zhu, P. P. Pande, and C. Grecu, "Performance evaluation of adaptive routing algorithms for achieving fault tolerance in noc fabrics," in ASAP, 2007.
[20]
J. Kim, D. Park, T. Theocharides, N. Vijaykrishnan, and C. R. Das, "A low latency router supporting adaptivity for on-chip interconnects," in DAC, 2005.
[21]
I. Walter, I. Cidon, R. Ginosar, and A. Kolodny, "Access regulation to hot-modules in wormhole nocs," in NOCS, pp. 137--148, May 2007.
[22]
R. Henia, A. Hamann, M. Jersak, R. Racu, K. Richter, and R. Ernst, "System level performance analysis - the symta/s approach," IEE Proceedings - Computers and Digital Techniques, vol. 152, pp. 148--166, Mar 2005.
[23]
E. A. Rambo and R. Ernst, "Worst-case communication time analysis of networks-on-chip with shared virtual channels," in DATE, 2015.
[24]
J. Diemer, P. Axer, and R. Ernst, "Compositional performance analysis in python with pyepa," in WATERS, jul 2012.
[25]
S. Schliecker and et al, "Providing accurate event models for the analysis of heterogeneous multiprocessor systems," in CODES+ISSS, pp. 185--190, ACM, 2008.
[26]
Y. Ben-Itzhak and et al., "Hnocs: Modular open-source simulator for heterogeneous nocs," in SAMOS, 2012.
[27]
R. Pellizzoni, P. Meredith, M.-Y. Nam, M. Sun, M. Caccamo, and L. Sha, "Handling mixed-criticality in soc-based real-time embedded systems," in EMSOFT, ACM, 2009.
[28]
A. do Carmo Lucas, H. Sahlbach, S. Whitty, S. Heithecker, and R. Ernst ACM TECS, 2009.
[29]
JEDEC, Arlington, Va, USA, JESD79-3F: DDR3 SDRAM Specification, July 2012.
[30]
Y. H. et al., "Proposal and quantitative analysis of the chstone benchmark program suite for practical c-based high-level synthesis," Journal of Information Processing, 2009.
[31]
R. Pellizzoni and et al., "A predictable execution model for cots-based embedded systems," in RTAS, 2011.
[32]
S. Tobuschat, P. Axer, R. Ernst, and J. Diemer, "Idamc: A noc for mixed criticality systems," in RTCSA, 2013.
- Multi-Path Scheduling for Multimedia Traffic in Safety Critical On-chip Network
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October 2016
118 pages
ISBN:9781450345439
DOI:10.1145/2993452
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Published: 01 October 2016
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