research-article

Silicon proof of the intelligent analog IP design flow for flexible automotive components

Authors:

T. Reich,

H. D. B. Prautsch,

U. Eichler,

R. BuhlAuthors Info & Claims

DATE '15: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition

Pages 403 - 404

Published: 09 March 2015 Publication History

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Abstract

In this brief paper we present the successful silicon validation of the Intelligent Analog IP (IIP) design flow applied to the design of a SMART sensor IC for automotive requirements. Using a library of reconfigurable and robust analog IP we fast create parameterized cells up to high complexity levels including the corresponding layouts. This allows us (1) to overcome time-consuming handcrafted analog re-design cycles, (2) to include the effects of layout parasitics into the optimization loop, and thus (3) to fast achieve different specifications even for multiple technologies. We show that the IIP design flow leads to a strong improvement of design efficiency, silicon performance, and yield.

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T. Reich, U. Eichler, K.-H. Rooch and R. Buhl, "Design of a 12-bit cyclic RSD ADC Sensor Interface IC using the Intelligent Analog IP Library," ANALOG 2013 - Entwicklung von Analogschaltungen mit CAE-Methoden, March 2013.

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Silicon proof of the intelligent analog IP design flow for flexible automotive components

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Published In

DATE '15: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition

March 2015

1827 pages

ISBN:9783981537048

General Chair:
Wolfgang Nebel
OFFIS & University of Oldenburg, DE
,
Program Chair:
David Atienza
EPFL, CH

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EDA Consortium

San Jose, CA, United States

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Published: 09 March 2015

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DATE '15

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EDAA
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SIGDA
Russian Acadamy of Sciences

DATE '15: Design, Automation and Test in Europe

March 9 - 13, 2015

Grenoble, France

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DATE '15 Paper Acceptance Rate 206 of 915 submissions, 23%;

Overall Acceptance Rate 518 of 1,794 submissions, 29%

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A programmable full clock rectifier and sample-and-hold amplifier for biomedical applications

2 to 23 GHz BiFET low noise amplifier design flow and implementations in 0.25 μm SiGe BiCMOS technology

Experimental implementation of $$\Delta \Sigma $$ΔΣAD modulator with dynamic analog components

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