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Low-latency wireless 3D NoCs via randomized shortcut chips

Published: 24 March 2014 Publication History

Abstract

In this paper, we demonstrate that we can reduce the communication latency significantly by inserting a fraction of randomness into a wireless 3D NoC (where CMOS wireless links are used for vertical inter-chip communication) when considering the physical constraints of the 3D design space. Towards this end, we consider two cases, namely 1) replacing existing horizontal 2D links in a wireless 3D NoC with randomized shortcut NoC links and 2) enabling full connectivity by adding a randomized NoC layer to a wireless 3D platform with partial or no horizontal connectivity. Consequently, the packet routing is optimized by exploiting both the existing and the newly added random NoC. At the same time, by adding randomly wired shortcut NoCs to a wireless 3D platform, a good balance can be established between the modularity of the design and the minimum randomness needed to achieve low latency, and experimental results show that by adding a random NoC chip to wireless 3D CMPs without built-in horizontal connectivity, the communication latency can be reduced by as much as 26.2% when compared to adding a 2D mesh NoC. Also, the application execution time and average flit transfer energy can be improved accordingly.

References

[1]
W. R. Davis et al., "Demystifying 3D ICs: The Pros and Cons of Going Vertical," IEEE Design and Test of Computers, vol. 22, no. 6, pp. 498--510, Nov. 2005.
[2]
N. Miura, H. Ishikuro, T. Sakurai, and T. Kuroda, "A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping," in Proceedings of the International Solid-State Circuits Conference (ISSCC'07), Feb. 2007, pp. 358--359.
[3]
S. Saito et al., "MuCCRA-Cube: a 3D Dynamically Reconfigurable Processor with Inductive-Coupling Link," in Proceedings of the Field-Programmable Logic and Applications (FPL'09), Sep. 2009, pp. 6--11.
[4]
M. D. Schroeder et al., "Autonet: A High-speed, Self-configuring Local Area Network Using Point-to-point Links," IEEE Journal on Selected Areas in Communications, vol. 9, pp. 1318--1335, Oct. 1991.
[5]
H. Matsutani, P. Bogdan, R. Marculescu, Y. Take, D. Sasaki, H. Zhang, M. Koibuchi, T. Kuroda, and H. Amano, "A Case for Wireless 3D NoCs for CMPs," in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'13), Jan. 2013, pp. 22--28.
[6]
M. Koibuchi, H. Matsutani, H. Amano, D. F. Hsu, and H. Casanova, "A Case for Random Shortcut Topologies for HPC Interconnects," in Proceedings of the International Symposium on Computer Architecture (ISCA'12), 2012, pp. 177--188.
[7]
A. Singla, C.-Y. Hong, L. Popa, and P. B. Godfrey, "Jellyfish: Networking Data Centers Randomly," in Proceedings of the USENIX conference on Networked Systems Design and Implementation (NSDI'12), Oct. 2012.
[8]
U. Y. Ogras and R. Marculescu, "It's a Small World After All: NoC Performance Optimization via Long-Range Link Insertion," IEEE Transactions on Very Large Scale Integration Systems, vol. 14, pp. 693--706, 2006.
[9]
A. Ganguly, K. Chang, S. Deb, P. P. Pande, B. Belzer, and C. Teuscher, "Scalable Hybrid Wireless Network-on-Chip Architectures for Multi-core Systems," IEEE Transactions on Computers, vol. 60, no. 10, pp. 1485--1502, Oct. 2011.
[10]
S. J. Hollis, C. Jackson, P. Bogdan, and R. Marculescu, "Exploiting Emergence in On-chip Interconnects," IEEE Transactions on Computers, Nov. 2012, (PrePrint).
[11]
D. J. Watts and S. H. Strogatz, "Collective Dynamics of 'Small-World' Networks," Nature, vol. 393, no. 6684, pp. 440--442, 1998.
[12]
H. Matsutani, Y. Take, D. Sasaki, M. Kimura, Y. Ono, Y. Nishiyama, M. Koibuchi, T. Kuroda, and H. Amano, "A Vertical Bubble Flow Network using Inductive-Coupling for 3-D CMPs," in Proceedings of the International Symposium on Networks-on-Chip (NOCS'11), May 2011, pp. 49--56.
[13]
T. D. Richardson, C. Nicopoulos, D. Park, V. Narayanan, Y. Xie, C. Das, and V. Degalahal, "A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks," in Proceedings of International Conference on VLSI Design (VLSID'06), Jan. 2006, pp. 657--664.
[14]
M. O. Agyeman, A. Ahmadinia, and A. Shahrabi, "Low Power Heterogeneous 3D Networks-on-Chip Architectures," in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS'11), Jul. 2011, pp. 533--538.
[15]
N. Binkert et al., "The gem5 Simulator," ACM SIGARCH Computer Architecture News, vol. 39, no. 2, pp. 1--7, May 2011.

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DATE '14: Proceedings of the conference on Design, Automation & Test in Europe
March 2014
1959 pages
ISBN:9783981537024

Sponsors

  • EDAA: European Design Automation Association
  • ECSI
  • EDAC: Electronic Design Automation Consortium
  • IEEE Council on Electronic Design Automation (CEDA)
  • The Russian Academy of Sciences: The Russian Academy of Sciences

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European Design and Automation Association

Leuven, Belgium

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Published: 24 March 2014

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DATE '14
Sponsor:
  • EDAA
  • EDAC
  • The Russian Academy of Sciences
DATE '14: Design, Automation and Test in Europe
March 24 - 28, 2014
Dresden, Germany

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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