Transistor-level gate model based statistical timing analysis considering correlations
Abstract
To increase the accuracy of static timing analysis, the traditional nonlinear delay models (NLDMs) are increasingly replaced by the more physical current source models (CSMs). However, the extension of CSMs into statistical models for statistical timing analysis is not easy. In this paper, we propose a novel correlation-preserving statistical timing analysis method based on transistor-level gate models. The correlations among signals and between process variations are fully accounted for. The accuracy and efficiency are obtained from statistical transistor-level gate models, evaluated using a smart Random Differential Equation (RDE)-based solver. The variational waveforms are available, allowing signal integrity checks and circuit optimization. The proposed algorithm is verified with standard cells, simple digital circuits and ISCAS benchmark circuits in a 45nm technology. The results demonstrate the high accuracy and speed of our algorithm.
References
[1]
J. F. Croix and D. F. Wong, "A fast and accurate technique to optimize characterization tables for logic sythesis," in DAC, 1997, pp. 337--340.
[2]
Synopsys. CCS timing white paper. {Online}. Available: www.synopsys.com/products/solutions/galaxy/ccs/cc_source
[3]
H. Fatemi, S. Nazarian, and M. Pedram, "Statistical logic cell delay analysis using a current-based model," in DAC, 2006, pp. 253--256.
[4]
A. Goel and S. Vrudhula, "Statistical waveform and current source based standard cell models for accurate timing analysis," in DAC, 2008, pp. 227--230.
[5]
B. Liu and A. B. Kahng, "Statistical gate level simulation via voltage controlled current source models," in BMAS Workshop, Sept. 2006, p. 23.
[6]
B. Liu, "Gate level statistical simulation based on parameterized models for process and signal variations," in ISQED, 2007, pp. 257--262.
[7]
C. Amin, C. Kashyap, N. Menezes, k. Killpack, and E. Chiprout, "A multi-port current source model for multiple-input switching effects in cmos library cells," in DAC 2006, June 2006, pp. 247--252.
[8]
P. Kulshreshtha, R. Palermo, M. Mortazavi, C. Bamji, and H. Yalcin, "Transistor-level timing analysis using embedded simulation," in ICCAD, 2000, pp. 344--349.
[9]
S. Raja, Varadi, M. Becer, and J. Geada, "Transistor level gate modeling for accurate and fast timing, noise, and power analysis," in DAC, 2008, pp. 456--461.
[10]
Q. Tang, A. Zjajo, M. Berkelaar, and N. P. van der Meijs, "Transistor level waveform evaluation for timing analysis," in VARI, 2010, pp. 1--6.
[11]
Q. Tang, A. Zjajo, M. Berkelaar, and N. P. van der Meijs, "RDE-based transistor-level gate simulation for statistical static timing analysis," in DAC, 2010, pp. 787--792.
[12]
Q. Tang, A. Zjajo, M. Berkelaar, and N. P. van der Meijs, "Statistical delay calculation with multiple input simultaneous switching," in ICICDT, 2011, pp. 1--4.
[13]
X. Li, P. Li, and L. T. Pileggi, "Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations," in ICCAD, 2005, pp. 806--812.
[14]
T. T. Soong, Random diffrential equations in science and engineering. New York: Academic Press, 1973.
[15]
J. P. Wilson and J. C. Gallant, TERRAIN analysis: principlea ans applications. John Wiley & Sons, Inc., Canada, 2002.
[16]
D. F. Morrison, Multivariate statistical methods. New York: McGraw-Hill, 1976.
[17]
Nangate 45nm open cell library. {Online}. Available: http://www.nangate.com/index.php?option=com_content&task=view&id=137&Itemid=137
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- Transistor-level gate model based statistical timing analysis considering correlations
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- EDAA: European Design Automation Association
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- EDAC: Electronic Design Automation Consortium
- SIGDA: ACM Special Interest Group on Design Automation
- IEEE CEDA
- The Russian Academy of Sciences: The Russian Academy of Sciences
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EDA Consortium
San Jose, CA, United States
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Published: 12 March 2012
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