research-article

SURF algorithm in FPGA: a novel architecture for high demanding industrial applications

Authors:

N. Battezzati,

S. Colazzo,

M. Maffione,

L. SenepaAuthors Info & Claims

DATE '12: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 161 - 162

Published: 12 March 2012 Publication History

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Abstract

Today many industrial applications require object recognition and tracking capabilities. Feature-based algorithms are well-suited for such operations and, among all, Speeded Up Robust Features (SURF) algorithm has been proved to achieve optimal results. However, when high-precision and real time requirements come together, a dedicated hardware is necessary to meet them. In this paper we present a novel architecture for implementing SURF algorithm in FPGA, along with experimental results for different industrial applications.

References

[1]

D. G. Lowe, "Distinctive image features from scale-invariant keypoints," International Journal of Computer Vision, vol. 60, pp. 91--110, 2004.

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[2]

K. Mikolajczyk et al., "A Comparison of Affine Region Detectors," Intern. Journal of Computer Vision, vol. 65, no. 1/2, pp. 43--72, 2005.

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[3]

H. Bay et al., "SURF: Speeded-Up Robust Features," Computer Vision and Image Understanding, vol. 110, no. 3, pp. 346--359, 2008.

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[4]

D. Bouris et al., "Fast and Efficient FPGA-Based Feature Detection Employing the SURF Algorithm," in Intern. Symposium on Field-Programmable Custom Computing Machines, 2010, pp. 3--10.

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[5]

M. Schaeferling et al., "Flex-SURF: A Flexible Architecture for FPGA-Based Robust Feature Extraction for Optical Tracking Systems," in Intern. Conference on Reconfigurable Computing and FPGAs, 2010.

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Index Terms

SURF algorithm in FPGA: a novel architecture for high demanding industrial applications
1. Applied computing
  1. Operations research
    1. Industry and manufacturing
      1. Command and control
2. Hardware
  1. Robustness
  2. Very large scale integration design
    1. Application-specific VLSI designs

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Published In

DATE '12: Proceedings of the Conference on Design, Automation and Test in Europe

March 2012

1690 pages

ISBN:9783981080186

General Chairs:
Wolfgang Rosenstiel
University of Tuebingen and edacentrum, DE
,
Enrico Macii
Politecnico di Torino, IT

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EDA Consortium

San Jose, CA, United States

Publication History

Published: 12 March 2012

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DATE '12

Sponsor:

EDAA
EDAC
SIGDA
The Russian Academy of Sciences

DATE '12: Design, Automation and Test in Europe

March 12 - 16, 2012

Dresden, Germany

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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FPGA-based module for SURF extraction

SoC based floating point implementation of differential evolution algorithm using FPGA

Floating-point FPGA: architecture and modeling

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Recommendations

FPGA-based module for SURF extraction

SoC based floating point implementation of differential evolution algorithm using FPGA

Floating-point FPGA: architecture and modeling

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