research-article

A novel si-tunnel FET based SRAM design for ultra low-power 0.3V V_DD applications

Authors:

K. Ramakrishnan,

N. Vijaykrishnan,

D. PradhanAuthors Info & Claims

ASPDAC '10: Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Pages 181 - 186

Published: 18 January 2010 Publication History

Abstract

Steep sub-threshold transistors are promising candidates to replace the traditional MOSFETs for sub-threshold leakage reduction. In this paper, we explore the use of Inter-Band Tunnel Field Effect Transistors (TFETs) in SRAMs at ultra low supply voltages. The uni-directional current conducting TFETs limit the viability of 6T SRAM cells. To overcome this limitation, 7T SRAM designs were proposed earlier at the cost of extra silicon area. In this paper, we propose a novel 6T SRAM design using Si-TFETs for reliable operation with low leakage at ultra low voltages. We also demonstrate that a functional 6T TFET SRAM design with comparable stability margins and faster performances at low voltages can be realized using proposed design when compared with the 7T TFET SRAM cell. We achieve a leakage reduction improvement of 700X and 1600X over traditional CMOS SRAM designs at V_DD of 0.3V and 0.5V respectively which makes it suitable for use at ultra-low power applications.

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Cited By

Naghizadeh SGholami M(2019)Two Novel Ultra-Low-Power SRAM Cells with Separate Read and Write PathCircuits, Systems, and Signal Processing10.1007/s00034-018-0858-938:1(287-303)Online publication date: 1-Jan-2019
https://dl.acm.org/doi/10.1007/s00034-018-0858-9
Sadrosadati MMirhosseini AEhsani SSarbazi-Azad HDrumond MFalsafi BAusavarungnirun RMutlu O(2018)LTRFACM SIGPLAN Notices10.1145/3296957.317321153:2(489-502)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3296957.3173211
Sadrosadati MMirhosseini AEhsani SSarbazi-Azad HDrumond MFalsafi BAusavarungnirun RMutlu OShen XTuck JBianchini RSarkar V(2018)LTRFProceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3173162.3173211(489-502)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3173162.3173211
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A novel si-tunnel FET based SRAM design for ultra low-power 0.3V V_DD applications
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Published In

cover image ACM Conferences

ASPDAC '10: Proceedings of the 2010 Asia and South Pacific Design Automation Conference

January 2010

920 pages

ISBN:9781605588377

General Chair:
Youn-Long Lin
National Tsing Hua University

Sponsors

TICD: TICD
SIGDA: ACM Special Interest Group on Design Automation
IEEE CAS

Publisher

IEEE Press

Publication History

Published: 18 January 2010

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Research-article

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ASPDAC '10

Sponsor:

TICD
SIGDA

ASPDAC '10: Asia and South Pacific Design Automation Conference

January 18 - 21, 2010

Taipei, Taiwan

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

Naghizadeh SGholami M(2019)Two Novel Ultra-Low-Power SRAM Cells with Separate Read and Write PathCircuits, Systems, and Signal Processing10.1007/s00034-018-0858-938:1(287-303)Online publication date: 1-Jan-2019
https://dl.acm.org/doi/10.1007/s00034-018-0858-9
Sadrosadati MMirhosseini AEhsani SSarbazi-Azad HDrumond MFalsafi BAusavarungnirun RMutlu O(2018)LTRFACM SIGPLAN Notices10.1145/3296957.317321153:2(489-502)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3296957.3173211
Sadrosadati MMirhosseini AEhsani SSarbazi-Azad HDrumond MFalsafi BAusavarungnirun RMutlu OShen XTuck JBianchini RSarkar V(2018)LTRFProceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3173162.3173211(489-502)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3173162.3173211
Gopireddy BSkarlatos DZhu WTorrellas J(2018)HetCoreProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00072(802-815)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00072
Rakshit JMohanram KWan RLam KGuo J(2017)Monolayer Transistor SRAMsACM Journal on Emerging Technologies in Computing Systems10.1145/296761313:2(1-28)Online publication date: 2-Mar-2017
https://dl.acm.org/doi/10.1145/2967613
Nunez JAvedillo M(2017)Comparison of TFETs and CMOS Using Optimal Design Points for Power–Speed TradeoffsIEEE Transactions on Nanotechnology10.1109/TNANO.2016.262926416:1(83-89)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1109/TNANO.2016.2629264
Hemmat MKamal MAfzali-Kusha APedram M(2017)Hybrid TFET-MOSFET circuitIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00157:C(11-19)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.11.001
Gupta NMakosiej AVladimirescu AAmara AAnghel CFanucci LTeich J(2016)3T-TFET bitcell based TFET-CMOS hybrid SRAM design for ultra-low power applicationsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2971891(361-366)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2971891
Sedighi BPalit IHu XNahas JNiemier MNebel WAtienza D(2015)A CNN-inspired mixed signal processor based on tunnel transistorsProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757079(1150-1155)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757079
Rakshit JWan RLam KGuo JMohanram K(2015)Monolayer transition metal dichalcogenide and black phosphorus transistors for low power robust SRAM designProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744872(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744872
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