research-article

Using non-volatile memory to save energy in servers

Authors:

David Roberts,

Taeho Kgil,

Trevor MudgeAuthors Info & Claims

DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 743 - 748

Published: 20 April 2009 Publication History

Get Access

Abstract

Recent breakthroughs in circuit and process technology have enabled new usage models for non-volatile memory technologies such as Flash and phase change RAM (PCRAM) in the general purpose computing environment. These technologies display high density and low power consumption as well as persistency that are appealing properties in a memory device. This paper summarizes our earlier work on improving NAND Flash based disk caches and extends it to consider PCRAM. We first present the primary challenges in reliably managing non-volatile memories such as NAND Flash, reviewing our past work on architectural support for Flash manageability. We then provide a preliminary analysis of how our current Flash manageability architecture may be simplified when we replace Flash with PCRAM. Our evaluations on PCRAM shows a potential for more than a 65% throughput improvement for a disk-intensive database workload. Although more detailed studies are needed, we conclude that PCRAM is a strong contender to replace Flash if it becomes cost-effective.

References

[1]

G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S. Shenoy, "Overview of candidate device technologies for storage-class memory," IBM Journal of Research and Development, vol. 52, no. 4, Sep 2008.

Digital Library

Google Scholar

[2]

F. Bedeschi, R. Fackenthal, C. Resta, E. M. Donz, M. Jagasivamani, E. C. Buda, F. Pellizzer, D. W. Chow, A. Cabrini, G. M. A. Calvi, R. Faravelli, A. Fantini, G. Torelli, D. Mills, R. Gastaldi, and G. Casagrande, "A bipolar-selected phase change memory featuring multi-level cell storage," JSSC, vol. 44, 2009.

Google Scholar

[3]

T. Kgil and T. Mudge, "Flashcache: a nand flash memory file cache for low power web servers," International Conference on Compilers, Architecture and Synthesis for Embedded Systems, 2006.

Digital Library

Google Scholar

[4]

T. Kgil, D. Roberts, and T. Mudge, "Improving NAND Flash based Disk Caches," in Proc. Int'l Symp. on Computer Architecture (ISCA), 2008.

Digital Library

Google Scholar

[5]

"Flex-OneNAND," http://www.samsung.com/global/business/semiconductor/products/fusionmemory/Products_FlexOneNAND.html.

Google Scholar

[6]

"Technical Note: TrueFFS Wear-Leveling Mechanism(TN-DOC-017)," http://www.embeddedfreebsd.org/Documents/TrueFFS_Wear_Leveling_Mechanism.pdf.

Google Scholar

[7]

L.-P. Chang, "On efficient wear-leveling for large-scale flash-memory storage systems," in 22nd ACM Symposium on Applied Computing (ACM SAC), 2007.

Digital Library

Google Scholar

[8]

L.-P. Chang and T.-W. Kuo, "Real-time garbage collection for flashmemory storage system in embedded systems," in ACM Transactions on Embedded Computing Systems, Vol 3, No. 4, 2004.

Digital Library

Google Scholar

[9]

G. Atwood and R. Bez, "Current status of chalcogenide phase change memory," Device Research Conference (DRC), 2005.

Google Scholar

[10]

T. Cho et al., "A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-mb single-level modes," IEEE Journal of Solid State Circuits, vol. 36, no. 11, Nov 2001.

Google Scholar

[11]

N. Binkert, R. Dreslinski, L. Hsu, K. Lim, A. Saidi, and S. Reinhardt, "The M5 simulator: Modeling networked systems," IEEE Micro, vol. 26, no. 4, pp. 52--60, Jul/Aug 2006.

Digital Library

Google Scholar

[12]

Y. Park, S.-H. Lim, C. Lee, and K. H. Park, "Pffs: A scalable flash memory file system for the hybrid architecture of phase-change ram and nand flash," SAC, Mar. 2008.

Digital Library

Google Scholar

Cited By

View all

Tschirhart PStevens JChishti ZLu SJacob B(2015)Bringing Modern Hierarchical Memory Systems Into FocusProceedings of the 2015 International Symposium on Memory Systems10.1145/2818950.2818975(179-190)Online publication date: 5-Oct-2015
https://dl.acm.org/doi/10.1145/2818950.2818975
Gutierrez ACieslak MGiridhar BDreslinski RCeze LMudge T(2014)Integrated 3D-stacked server designs for increasing physical density of key-value storesACM SIGARCH Computer Architecture News10.1145/2654822.254195142:1(485-498)Online publication date: 24-Feb-2014
https://dl.acm.org/doi/10.1145/2654822.2541951
Gutierrez ACieslak MGiridhar BDreslinski RCeze LMudge T(2014)Integrated 3D-stacked server designs for increasing physical density of key-value storesACM SIGPLAN Notices10.1145/2644865.254195149:4(485-498)Online publication date: 24-Feb-2014
https://dl.acm.org/doi/10.1145/2644865.2541951
Show More Cited By

Using non-volatile memory to save energy in servers
1. General and reference
  1. Cross-computing tools and techniques
2. Hardware
  1. Integrated circuits

Recommendations

Energy optimization for multi-level cell non-volatile memory using state remapping

Non-volatile Memory (NVM) is emerging as a promising technology to build future main memory or cache. Multi-level cell (MLC) NVM that stores multiple bits in a single cell has been developed in recent years. Different NVM technology has its own writing ...
On the Energy-Efficiency of Byte-Addressable Non-Volatile Memory
Non-volatile memory (NVM) technology holds promise to replace SRAM and DRAM at various levels of the memory hierarchy. The interest in NVM is motivated by the difficulty faced in scaling DRAM beyond 22<inline-formula><tex-math> $\:$</tex-math><...
Redesign the Memory Allocator for Non-Volatile Main Memory
Special Issue on Hardware and Algorithms for Learning On-a-chip and Special Issue on Alternative Computing Systems

The non-volatile memory (NVM) has the merits of byte-addressability, fast speed, persistency and low power consumption, which make it attractive to be used as main memory. Commonly, user process dynamically acquires memory through memory allocators. ...

Comments

Information & Contributors

Information

Published In

DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe

April 2009

1776 pages

ISBN:9783981080155

General Chairs:
Luca Benini
University of Bologna, IT
,
Giovanni De Micheli
EPFL, CH
,
Program Chairs:
Bashir Al-Hashimi
University of Southampton, UK
,
Wolfgang Mueller
University of Paderborn, DE

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 20 April 2009

Check for updates

Qualifiers

Research-article

Conference

DATE '09

Sponsor:

EDAA
EDAC
SIGDA
The Russian Academy of Sciences

DATE '09: Design, Automation and Test in Europe

April 20 - 24, 2009

Nice, France

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Upcoming Conference

DATE '25

Sponsor:
sigda

Design, Automation and Test in Europe

March 31 - April 2, 2025

Lyon , France

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

10
Total Citations
View Citations
248
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 10 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Tschirhart PStevens JChishti ZLu SJacob B(2015)Bringing Modern Hierarchical Memory Systems Into FocusProceedings of the 2015 International Symposium on Memory Systems10.1145/2818950.2818975(179-190)Online publication date: 5-Oct-2015
https://dl.acm.org/doi/10.1145/2818950.2818975
Gutierrez ACieslak MGiridhar BDreslinski RCeze LMudge T(2014)Integrated 3D-stacked server designs for increasing physical density of key-value storesACM SIGARCH Computer Architecture News10.1145/2654822.254195142:1(485-498)Online publication date: 24-Feb-2014
https://dl.acm.org/doi/10.1145/2654822.2541951
Gutierrez ACieslak MGiridhar BDreslinski RCeze LMudge T(2014)Integrated 3D-stacked server designs for increasing physical density of key-value storesACM SIGPLAN Notices10.1145/2644865.254195149:4(485-498)Online publication date: 24-Feb-2014
https://dl.acm.org/doi/10.1145/2644865.2541951
Park SMaeng MPark KPark K(2014)Adaptive wear-leveling algorithm for PRAM main memory with a DRAM bufferACM Transactions on Embedded Computing Systems10.1145/255842713:4(1-25)Online publication date: 10-Mar-2014
https://dl.acm.org/doi/10.1145/2558427
Lee SKim JLee MLee HEom YKim DKim SLee SHanzo KIsmail R(2014)Last block logging mechanism for improving performance and lifetime on SCM-based file systemProceedings of the 8th International Conference on Ubiquitous Information Management and Communication10.1145/2557977.2558014(1-4)Online publication date: 9-Jan-2014
https://dl.acm.org/doi/10.1145/2557977.2558014
Gutierrez ACieslak MGiridhar BDreslinski RCeze LMudge TBalasubramonian RDavis AAdve S(2014)Integrated 3D-stacked server designs for increasing physical density of key-value storesProceedings of the 19th international conference on Architectural support for programming languages and operating systems10.1145/2541940.2541951(485-498)Online publication date: 24-Feb-2014
https://dl.acm.org/doi/10.1145/2541940.2541951
Baek SChoi JLee DNoh S(2013)Energy-efficient and high-performance software architecture for storage class memoryACM Transactions on Embedded Computing Systems10.1145/2442116.244213112:3(1-22)Online publication date: 8-Apr-2013
https://dl.acm.org/doi/10.1145/2442116.2442131
Hu JXue CZhuge QTseng WSha E(2013)Write activity reduction on non-volatile main memories for embedded chip multiprocessorsACM Transactions on Embedded Computing Systems10.1145/2442116.244212712:3(1-27)Online publication date: 8-Apr-2013
https://dl.acm.org/doi/10.1145/2442116.2442127
Luo HZhuge QShi LLi JSha E(2013)Accurate age counter for wear leveling on non-volatile based main memoryDesign Automation for Embedded Systems10.1007/s10617-014-9141-x17:3-4(543-564)Online publication date: 1-Sep-2013
https://dl.acm.org/doi/10.1007/s10617-014-9141-x
Hu JXue CTseng WHe YQiu MSha ESapatnekar S(2010)Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputationProceedings of the 47th Design Automation Conference10.1145/1837274.1837363(350-355)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837363

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Recommendations

Energy optimization for multi-level cell non-volatile memory using state remapping

On the Energy-Efficiency of Byte-Addressable Non-Volatile Memory

Redesign the Memory Allocator for Non-Volatile Main Memory

Comments

Information

Published In

Sponsors

Publisher

Publication History

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations