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Random current testing for CMOS logic circuits by monitoring a dynamic power supply current

Published: 01 November 1992 Publication History
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References

[1]
W.Maly and P.Nigh,"Built-In current testing -feasibility study", Proc. Int'l Conf. on Computer- Aided Design, pp.340-343(1988).
[2]
P. Nigh and W. Maly,"Test generation for current testing," IEEE Design & Test of Computers, Vol.7, No.2, pp.26-38(Feb. 1990).
[3]
W. Maly,"Current testing," Proc. Int'l Test Conf., p.257(1990).
[4]
Y. Miura, Y. Wada and K. Kinoshita,"Generation of test sequences for current testing," Proc. Pacific RIM Int'l Symp. on Fault Tolerant Systems, pp.1294-1300(1991).
[5]
E. Vandris and G. Sobelman,"A mixed function/ It~ testing methodology for CMOS transistor faults," Proc. Int'l Test Conf., pp.608-614(1991).
[6]
H. Eiki, K. Inagaki and S. Yajima,"Autonomous testing and its application to testable design of logic circuits," Dig. of FTCS10, pp.173-178(1980).
[7]
F.Bgrlez and H. Fujiwam,"Neutral netlist of ten combinational benchmark circuits and a target translator in FORTRAN," Proc. Int'l Symp. Circuits and Systems(1985).
[8]
H. Fujiwara and T. Shimono,"On the acceleration of test generation algorithms," IEEE Trans. Comput., Vo1.C-32, No.12, pp.1137-1144(Dec.1983).

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      cover image ACM Conferences
      EURO-DAC '92: Proceedings of the conference on European design automation
      November 1992
      765 pages
      ISBN:0818627808

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      IEEE Computer Society Press

      Washington, DC, United States

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      Published: 01 November 1992

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