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SIESTA: a multi-facet scan design system

Published: 01 November 1992 Publication History
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References

[1]
M. Abramovici, M.A. Breuer, and A.D. Friedman. Digital Systems Testing and Testable Design. W.H. Freeman and Company, 1990.
[2]
E.B. Eichelberger and T.W. Williams. A logic design structure for LSI testability. J. Design Automation and Fault- Tolerant Computing, 2(2):165-178, 1978.
[3]
R. Gupta, R. Gupta, and M. A. Breuer. The BAL- LAST methodology for structured partial scan design. 1EEE Trans. on Computers, 39(14):538-543, April 1990.
[4]
K.-T. Cheng and V.D. Agrawal. A partial scan method for sequential circuits with feedback. 1EEE Trans. on Computers, 39(4):544-548, April 1990.
[5]
R. Gupta. Advanced Serial Scan Design for Testability. Ph.D. thesis, Univ. of Southern California, Dept. of Electrical Engineering-Systems, 1991. CEnt Technical Report 91-10.
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R. Gupta, W. H. Cheng, R. Gupta, I. Hardonag, and M. A. Breuer. An object-oriented VLSI CAD framework: A case study in rapid prototyping. 1EEE Computer, pages 28-37, May 1989.
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R. Gupta, R. Srinivasan, and M.A. Breuer. CRETE: Hierarchical reorganization of circuits for DFT and BIST. 1EEE Design & Test, pages 49-57~ September 1991.
[8]
S. Narayanan, C.A. Njinda, and M.A. Breuer. Optimal sequencing of scan registers. Accepted for publication in lnt'l Test Conference, September 1992.
[9]
R. Gupta and M.A. Breuer. Ordering storage elements in a single scan chain, in Proc. 1CCAD, 1991.
[10]
P.P. Fasang, J. P. Shen, M. A. Schuette, and W. A. Gwaltney. Automated design for testability of semicustom integrated circuits. In Proc., lnt'l Test Conf., pages 558-564, November 1985.
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S. Narayanan, It. Cupta, and M.A. Breu,~r. Optimal configuring of multiple scan chains. Accepted for publication in 1EEE Trans. on Computers.

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cover image ACM Conferences
EURO-DAC '92: Proceedings of the conference on European design automation
November 1992
765 pages
ISBN:0818627808

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 November 1992

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