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Verification of digital circuits based on formal semantics of a hardware description language

Published: 01 November 1992 Publication History
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References

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P.Amblard, P.Caspi, N.Halbwachs: "Use of time functions to describe and explain circuit behavior," lEE Proceedings, Voi.133, Pt.E, No.5, 271-275, 1986
[2]
R.S. Boyer, J.S.Moore: "A Computational Logic Handbook," Academic Press, 1988
[3]
D.Borrione, J.-L.Paillet, L.Pierre: "Formal Verification of CASCADE descriptions," The Fusion of Hardware Design,and Verification, G.J.Milne (ed.), Noah-Holland, 185-210, 1988
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R.E.Bryant: "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. on Computers, Vol. C-35, No. 8, 677-691, August, 1985
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H.Eveking: "Automatic Verification of Extensions of Hardware Descriptions," Proc. CAV 90, E.M.Clarke & R.P.Kurshan (eds.), 2-12, 1990
[6]
M.Gordon: "HOL - A Machine Oriented Formulation of Higher Order Logic," University of Cambridge, Computer Laboratory, Technical Report no. 68, 1985
[7]
W.Grass: "VERENA - A CAD tool for designing guaranteed correct logic circuits," Proc. 2nd ABAKUS workshop, Innsbruck-Igls, Austria, 1988
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F.K.Hanna, N.Daeche: "Specification and Verification using Higher Order Logic," Proc. CHDL 85, Kommen and Moto-oka (eds.), North Holland, 1985
[9]
M.Mutz: "Formal verification of sequential circuits with VERENA: a case study," Proc. Correct Hardware Design Methodologies, Turin, Italy, P.Prinetto and P.Camurati (eds.), 29-50, North-Holland, 1992
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M.Mutz: "Using the HOL prove assistant for proving the correctness of term rewriting rules reducing terms of sequential behavior,"Proc. CAV 91, K.G.Larsen & A.Skou (eds.), Aalborg, Denmark, Springer LNCS, 277-287, 1992
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M.Nesi: "Mechanizing a Proof by Induction of Process Algebra Specifications in Higher Order Logic," Proc. CA V 91, K.G.Larsen & A.Skou (eds.), Aalborg, Denmark, Springer LNCS, 288-298, 1992
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D.K.Probst, H.F.Li: "Using Partial-Order Semantics to Avoid the State Explosion Problem in Asynchronous Systems," Proc. CAV 90, E.M.Clarke & R.P.Kurshan (eds.), 146-155, 1990
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S.R.Ramirez Chavez: "Formal proof of the cascading properties of a parallel sorting circuit," Proc. IMEC-IFIP Int. Workshop on Applied Formal Methods for Correct VLSI Design, L.J.M.Claesen (ed.), Houlthalen Belgium, 338-346, 1989

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cover image ACM Conferences
EURO-DAC '92: Proceedings of the conference on European design automation
November 1992
765 pages
ISBN:0818627808

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 November 1992

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