Article

Polymorphic On-Chip Networks

Authors:

Martha Mercaldi Kim,

Todd AustinAuthors Info & Claims

ISCA '08: Proceedings of the 35th Annual International Symposium on Computer Architecture

Pages 101 - 112

https://doi.org/10.1109/ISCA.2008.25

Published: 01 June 2008 Publication History

Abstract

As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We begin this study with an area-performance analysis of the interconnect design space. We find that there is no single network design that yields optimal performance across a range of traffic patterns. This indicates that there is an opportunity to gain performance by customizing the interconnect to a particular application or workload. We propose polymorphic on-chip networks to enable per-application network customization. This network can be configured prior to application runtime, to have the topology and buffering of arbitrary network designs. This paper proposes one such polymorphic network architecture. We demonstrate its modes of configurability, and evaluate the polymorphic network architecture design space, producing polymorphic fabrics that minimize the network area overhead. Finally, we expand the network on chip design space to include a polymorphic network design, showing that a single polymorphic network is capable of implementing all of the pareto optimal fixed-network designs.

References

[1]

P. Abad, V. Puente, J. A. Gregorio, and P. Prieto. Rotary router: an efficient architecture for CMP interconnection networks. ACM SIGARCH Computer Architecture News, 35(2):116-125, 2007.

Digital Library

[2]

A. Abnous, H. Zhang, M. Wan, G. Varghese, V. Prabhu, and J. Rabaey. The pleiades architecture. The Application of Programmable DSPs in Mobile Communications, pages 327- 360, 2002.

[3]

J. Balfour and W. J. Dally. Design tradeoffs for tiled CMP on-chip networks. In Proc. of the International Conference on Supercomputing, pages 187-198, 2006.

Digital Library

[4]

K. Constantinides, S. Plaza, B. Z. Jason Blome, V. Bertacco, S. Mahlke, T. Austin, and M. Orshansky. Bulletproof: A defecttolerant CMP switch architecture. In Proc. of the International Symposium on High-Performance Computer Architecture , pages 5-16, 2006.

[5]

M. Coppola, R. Locatelli, G. Maruccia, L. Pieralisi, and A. Scandurra. Spidergon: a novel on-chip communication network. In Proc. of the International Symposium on System-on-Chip , page 15, 2004.

[6]

W. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2003.

Digital Library

[7]

W. J. Dally. Virtual-channel flow control. In Proc. of the International Symposium on Computer Architecture, pages 60- 68, 1990.

Digital Library

[8]

W. J. Dally and J. W. Poulton. Digital systems engineering. Cambridge University Press, New York, NY, USA, 1998.

Digital Library

[9]

W. J. Dally and C. L. Seitz. Deadlock-free message routing in multiprocessor interconnection networks. IEEE Transactions on Computers, 36(5):547-553, 1987.

Digital Library

[10]

J. D. Davis, J. Laudon, and K. Olukotun. Maximizing CMP throughput with mediocre cores. In Proc. of the International Conference on Parallel Architectures and Compilation Techniques , pages 51-62, 2005.

Digital Library

[11]

C. Ebeling, D. C. Cronquist, and P. Franklin. RaPiD - re-configurable pipelined datapath. In Booktitle of the International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, pages 126-135, 1996.

Digital Library

[12]

C. Grecu and M. Jones. Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Transactions on Computers, 54(8):1025-1040, 2005.

Digital Library

[13]

J. Hu, U. Y. Ogras, and R. Marculescu. System-level buffer allocation for application-specific networks-on-chip router design. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 25(12):2919-2933, December 2006.

Digital Library

[14]

J. Huh, D. Burger, and S. W. Keckler. Exploring the design space of future CMPs. In Proc. of the International Conference on Parallel Architectures and Compilation Techniques, pages 199-210, 2001.

Digital Library

[15]

International technology roadmap for semiconductors. Semiconductor Industry Association, http://public.itrs.net/, 2006.

[16]

A. Jalabert, S. Murali, L. Benini, and G. D. Micheli. xpipesCompiler: A tool for instantiating application specific networks on chip. In Proc. of the Conference on Design, Automation and Test in Europe, page 20884, 2004.

Digital Library

[17]

J. Kim, W. J. Dally, and D. Abts. Flattened butterfly topology for on-chip networks. In Proc. of the International Symposium on Microarchitecture, pages 172-182, 2007.

Digital Library

[18]

N. Kirman, M. Kirman, R. K. Dokania, J. F. Martinez, A. B. Apsel, M. A. Watkins, and D. H. Albonesi. Leveraging optical technology in future bus-based chip multiprocessors. In Proc. of the International Symposium on Microarchitecture, pages 492-503, 2006.

Digital Library

[19]

A. Kumar, L.-S. Peh, P. Kundu, and N. K. Jha. Express virtual channels: towards the ideal interconnection fabric. In Proc. of the International Symposium on Computer Architecture, pages 150-161, 2007.

Digital Library

[20]

C. E. Leiserson, Z. S. Abuhamdeh, D. C. Douglas, C. R. Feynman, M. N. Ganmukhi, J. V. Hill, D. Hillis, B. C. Kuszmaul, M. A. S. Pierre, D. S. Wells, M. C. Wong, S.-W. Yang, and R. Zak. The network architecture of the connection machine CM-5 (extended abstract). In Proc. of the Symposium on Parallel Algorithms and Architectures, pages 272-285, 1992.

Digital Library

[21]

R. Mullins, A. West, and S. Moore. Low-latency virtual-channel routers for on-chip networks. In Proc. of the International Symposium on Computer Architecture, page 188, 2004.

Digital Library

[22]

S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. D. Micheli, and L. Raffo. Designing application-specific networks on chips with floorplan information. In Proc. of the International Conference on Computer-Aided Design, pages 355-362, 2006.

Digital Library

[23]

S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. D. Micheli, and L. Raffo. Designing application-specific networks on chips with floorplan information. In Proc. of the International Conference on Computer-Aided Design, pages 355-362, 2006.

Digital Library

[24]

H. Singh, G. Lu, E. Filho, R. Maestre, M.-H. Lee, F. Kurdahi, and N. Bagherzadeh. MorphoSys: case study of a reconfigurable computing system targeting multimedia applications. In Proc. of the Conference on Design Automation, pages 573- 578, 2000.

Digital Library

[25]

H. Wang, L.-S. Peh, and S. Malik. Power-driven design of router microarchitectures in on-chip networks. In Proc. of the International Symposium on Microarchitecture, pages 105- 115, 2003.

Digital Library

[26]

A. Yoo, E. Chow, K. Henderson, W. McLendon, B. Hendrickson, and U. Catalyurek. A scalable distributed parallel breadth-first search algorithm on bluegene/l. In Proc. of the Conference on Supercomputing, page 25, 2005.

Digital Library

Cited By

He XChen KFeng SKim HBlaauw DDreslinski RMudge TKloeckner AMoreira J(2022)Squaring the circleProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1145/3559009.3569665(148-159)Online publication date: 8-Oct-2022
https://dl.acm.org/doi/10.1145/3559009.3569665
Zheng HWang KLouri ALi Z(2020)A versatile and flexible chiplet-based system design for heterogeneous manycore architecturesProceedings of the 57th ACM/EDAC/IEEE Design Automation Conference10.5555/3437539.3437654(1-6)Online publication date: 20-Jul-2020
https://dl.acm.org/doi/10.5555/3437539.3437654
Nematollahi NSadrosadati MFalahati HBarkhordar MDrumond MSarbazi-Azad HFalsafi B(2020)Efficient Nearest-Neighbor Data Sharing in GPUsACM Transactions on Architecture and Code Optimization10.1145/342998118:1(1-26)Online publication date: 30-Dec-2020
https://dl.acm.org/doi/10.1145/3429981
Show More Cited By

Index Terms

Polymorphic On-Chip Networks

Recommendations

Polymorphic On-Chip Networks

As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We begin this study with an area-performance analysis of the interconnect design ...
Triplet-based topology for on-chip networks

Most CMPs use on-chip network to connect cores and tend to integrate more simple cores on a single die. As the number of cores increases, on-chip network will play an important role in the performance of future CMPs. Due to the tradeoff between the ...
Low-cost router microarchitecture for on-chip networks
MICRO 42: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture

On-chip networks are critical to the scaling of future multi-core processors. The challenge for on-chip network is to reduce the cost including power consumption and area while providing high performance such as low latency and high bandwidth. Although ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ISCA '08: Proceedings of the 35th Annual International Symposium on Computer Architecture

June 2008

449 pages

ISBN:9780769531748

ACM SIGARCH Computer Architecture News Volume 36, Issue 3
June 2008
449 pages
ISSN:0163-5964
DOI:10.1145/1394608
Issue’s Table of Contents

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 June 2008

Check for updates

Author Tags

Qualifiers

Article

Conference

ISCA08

Sponsor:

SIGARCH

ISCA08: The 35th Annual International Symposium on Computer Architecture

June 21 - 25, 2008

Acceptance Rates

ISCA '08 Paper Acceptance Rate 37 of 259 submissions, 14%;

Overall Acceptance Rate 543 of 3,203 submissions, 17%

Upcoming Conference

ISCA '25

Sponsor:
sigarch

The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

32
Total Citations
View Citations
718
Total Downloads

Downloads (Last 12 months)14
Downloads (Last 6 weeks)3

Reflects downloads up to 05 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

He XChen KFeng SKim HBlaauw DDreslinski RMudge TKloeckner AMoreira J(2022)Squaring the circleProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1145/3559009.3569665(148-159)Online publication date: 8-Oct-2022
https://dl.acm.org/doi/10.1145/3559009.3569665
Zheng HWang KLouri ALi Z(2020)A versatile and flexible chiplet-based system design for heterogeneous manycore architecturesProceedings of the 57th ACM/EDAC/IEEE Design Automation Conference10.5555/3437539.3437654(1-6)Online publication date: 20-Jul-2020
https://dl.acm.org/doi/10.5555/3437539.3437654
Nematollahi NSadrosadati MFalahati HBarkhordar MDrumond MSarbazi-Azad HFalsafi B(2020)Efficient Nearest-Neighbor Data Sharing in GPUsACM Transactions on Architecture and Code Optimization10.1145/342998118:1(1-26)Online publication date: 30-Dec-2020
https://dl.acm.org/doi/10.1145/3429981
Pal SFeng SPark DKim SAmarnath AYang CHe XBeaumont JMay KXiong YKaszyk KMorton JSun JO'Boyle MCole MChakrabarti CBlaauw DKim HMudge TDreslinski RSarkar VKim H(2020)TransmuterProceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques10.1145/3410463.3414627(175-190)Online publication date: 30-Sep-2020
https://dl.acm.org/doi/10.1145/3410463.3414627
Hesse RJerger N(2016)Hierarchical Clustering for On-Chip NetworksProceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems10.1145/2857058.2857064(1-6)Online publication date: 18-Jan-2016
https://dl.acm.org/doi/10.1145/2857058.2857064
Mehrvarzy PModarressi MSarbazi-Azad H(2016)Power- and performance-efficient cluster-based network-on-chip with reconfigurable topologyMicroprocessors & Microsystems10.1016/j.micpro.2016.03.00446:PB(122-135)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1016/j.micpro.2016.03.004
Kannan AJerger NLoh GPrvulovic M(2015)Enabling interposer-based disintegration of multi-core processorsProceedings of the 48th International Symposium on Microarchitecture10.1145/2830772.2830808(546-558)Online publication date: 5-Dec-2015
https://dl.acm.org/doi/10.1145/2830772.2830808
Modarressi MTeimouri NSarbazi-azad H(2015)Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut pathsIntegration, the VLSI Journal10.1016/j.vlsi.2014.10.00350:C(193-204)Online publication date: 1-Jun-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2014.10.003
Büter WOsewold CGregorek DGarcía-Ortiz AFettweis GNebel W(2014)DCMProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617052(1-4)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2617052
Jerger NKannan ALi ZLoh GFlautner KWenisch TOzer EFerdman M(2014)NoC Architectures for Silicon Interposer SystemsProceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2014.61(458-470)Online publication date: 13-Dec-2014
https://dl.acm.org/doi/10.1109/MICRO.2014.61
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents