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Concurrent core test for SOC using shared test set and scan chain disable

Authors:

Hideo ItoAuthors Info & Claims

DATE '06: Proceedings of the conference on Design, automation and test in Europe: Proceedings

Pages 1045 - 1050

Published: 06 March 2006 Publication History

Abstract

A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. Prior to test, the test sets corresponding to cores under test (CUT) are merged by using the proposed merging algorithm to obtain a shared test set with minimum size. During test, the on-chip scan chain disable signal (SCDS) generator is employed to retrieve the original test vectors from the shared test set. The approach is non-intrusive and automatic test pattern generator (ATPG) independent. Moreover, the approach can reduce test cost further by combining with general test compression/decompression technique. Experimental results for ISCAS 89 benchmark circuits have proven the efficiency of the proposed approach.

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Cited By

Wang SWang RChakrabarty KTahoori M(2018)Multicast Testing of Interposer-Based 2.5D ICsACM Transactions on Design Automation of Electronic Systems10.1145/317787923:3(1-25)Online publication date: 23-Feb-2018
https://dl.acm.org/doi/10.1145/3177879
Larsson ALarsson EEles PPeng ZLauwereins RMadsen J(2007)Optimized integration of test compression and sharing for SOC testingProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266411(207-212)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266411
Zhou QBalakrishnan KLauwereins RMadsen J(2007)Test cost reduction for SoC using a combined approach to test data compression and test schedulingProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266377(39-44)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266377

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Information

Published In

cover image Guide Proceedings

DATE '06: Proceedings of the conference on Design, automation and test in Europe: Proceedings

March 2006

1390 pages

ISBN:3981080106

General Chair:
Georges Gielen
KU Leuven, BE

Sponsors

EDAA: European Design Automation Association
The EDA Consortium
IEEE-CS\DATC: The IEEE Computer Society

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 06 March 2006

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DATE '06 Paper Acceptance Rate 267 of 834 submissions, 32%;

Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Wang SWang RChakrabarty KTahoori M(2018)Multicast Testing of Interposer-Based 2.5D ICsACM Transactions on Design Automation of Electronic Systems10.1145/317787923:3(1-25)Online publication date: 23-Feb-2018
https://dl.acm.org/doi/10.1145/3177879
Larsson ALarsson EEles PPeng ZLauwereins RMadsen J(2007)Optimized integration of test compression and sharing for SOC testingProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266411(207-212)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266411
Zhou QBalakrishnan KLauwereins RMadsen J(2007)Test cost reduction for SoC using a combined approach to test data compression and test schedulingProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266377(39-44)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266377

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