Article

A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification

Authors:

John Dielissen,

Om Prakash Gangwal,

Santiago Gonzalez Pestana,

Andrei Radulescu,

Edwin RijpkemaAuthors Info & Claims

DATE '05: Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Pages 1182 - 1187

https://doi.org/10.1109/DATE.2005.11

Published: 07 March 2005 Publication History

Abstract

Systems on chip (SOC) are composed of intellectual property blocks (IP) and interconnect. While mature tooling exists to design the former, tooling for interconnect design is still a research area. In this paper we describe an operational design flow that generates and configures application-specific network on chip (NOC) instances, given application communication requirements. The NOC can be simulated in SystemC and RTL VHDL. An independent performance verification tool verifies analytically that the NOC instance (hardware) and its configuration (software) together meet the application performance requirements. The Æthereal NOC's guaranteed performance is essential to replace time-consuming simulation by fast analytical performance validation. As a result, application-specific NOCs that are guaranteed to meet the application's communication requirements are generated and verified in minutes, reducing the number of design iterations. A realistic MPEG SOC example substantiates our claims.

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Cited By

Beechu NMoodabettu Harishchandra VYernad Balachandra N(2018)Hardware implementation of fault tolerance NoC core mappingTelecommunications Systems10.1007/s11235-017-0412-268:4(621-630)Online publication date: 1-Aug-2018
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Gholami SSarjoughian H(2017)Modeling and verification of network-on-chip using constrained-DEVSProceedings of the Symposium on Theory of Modeling & Simulation10.5555/3108905.3108914(1-12)Online publication date: 23-Apr-2017
https://dl.acm.org/doi/10.5555/3108905.3108914
Hesham SRettkowski JGoehringer DAbd El Ghany M(2017)Survey on Real-Time Networks-on-ChipIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2016.262361928:5(1500-1517)Online publication date: 1-May-2017
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Index Terms

A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification

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Published In

cover image ACM Conferences

DATE '05: Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

March 2005

630 pages

ISBN:0769522882

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society

United States

Publication History

Published: 07 March 2005

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DATE05: Design, Automation and Test in Europe

March 7 - 11, 2005

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Beechu NMoodabettu Harishchandra VYernad Balachandra N(2018)Hardware implementation of fault tolerance NoC core mappingTelecommunications Systems10.1007/s11235-017-0412-268:4(621-630)Online publication date: 1-Aug-2018
https://dl.acm.org/doi/10.1007/s11235-017-0412-2
Gholami SSarjoughian H(2017)Modeling and verification of network-on-chip using constrained-DEVSProceedings of the Symposium on Theory of Modeling & Simulation10.5555/3108905.3108914(1-12)Online publication date: 23-Apr-2017
https://dl.acm.org/doi/10.5555/3108905.3108914
Hesham SRettkowski JGoehringer DAbd El Ghany M(2017)Survey on Real-Time Networks-on-ChipIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2016.262361928:5(1500-1517)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TPDS.2016.2623619
Becchu NHarishchandra VYernad Balachandra N(2017)System level fault-tolerance core mapping and FPGA-based verification of NoCMicroelectronics Journal10.1016/j.mejo.2017.09.01070:C(16-26)Online publication date: 1-Dec-2017
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Romanov AIvannikov A(2016)SystemC NoC simulation as the alternative to the HDL and high-level modelingProceedings of the 18th Conference of Open Innovations Association FRUCT10.1109/FRUCT-ISPIT.2016.7561540(285-290)Online publication date: 25-Apr-2016
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Boussadi MTixier TLandrault ADerutin J(2016)HNCPMicroprocessors & Microsystems10.1016/j.micpro.2016.10.00547:PB(333-346)Online publication date: 1-Nov-2016
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Lee JLi SKim HYalamanchili S(2013)Adaptive virtual channel partitioning for network-on-chip in heterogeneous architecturesACM Transactions on Design Automation of Electronic Systems10.1145/250490618:4(1-28)Online publication date: 25-Oct-2013
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Anagnostopoulos IBartzas AKathareios GSoudris DRosenstiel WMacii E(2012)A divide and conquer based distributed run-time mapping methodology for many-core platformsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492735(111-116)Online publication date: 12-Mar-2012
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Manevich RCidon IKolodny A(2012)Handling global traffic in future CMP NoCsProceedings of the International Workshop on System Level Interconnect Prediction10.1145/2347655.2347671(40-47)Online publication date: 3-Jun-2012
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