Search Results (251)

The complex resistivity (CR) measurement constitutes a practical methodology for investigating the internal structures of rocks and ores alongside their mineralogical compositions and the chemical properties of fluids. However, during complex resistivity testing, particularly at high frequencies, the leakage current caused by the distributed capacitance of the instrument’s acquisition channels reduces the measurement accuracy. Additionally, the contact impedance of the measuring devices and the electromagnetic coupling effects of the measurement cables further affect the complex resistivity test results of samples. To accurately characterize samples’ intrinsic induced polarization (IP) properties, we developed a broadband complex resistivity measurement system (1 mHz–100 kHz) for rocks and ores, comprising a complex resistivity analyzer and a sample holder, employing the four-electrode method. In this study, we establish a circuit model for the measurement system to analyze the influence of the distributed capacitance of the acquisition channels on the test results at elevated frequencies. We derive the error terms inherent in the instrument’s measurements across various circuit design configurations and propose a novel method for calculating the distributed capacitance of the instrument’s acquisition channels, the parasitic capacitance of the sampling resistor, and for calibrating data by reversing the polarity of the excitation signal. Furthermore, we investigate the effect of contact impedance within the measurement setup on test results and design two sample-testing devices. Through extensive testing on multiple circuit models and samples, the system achieves an accuracy of up to 1% within the 10 MΩ range. Its overall performance surpasses that of the Solartron 1260A impedance analyzer and traditional signal source forward connection calibration methods. This advancement holds significant implications for complex resistivity measurements and the study of rock physical properties. Full article

This paper presents a novel high-precision 11-bit single-slope/successive approximation register analog-to-digital converter (SS/SAR ADC) architecture specifically designed for CMOS image sensors (CISs). The proposed design solves critical challenges in conventional ADCs by utilizing only two reference voltages, thereby minimizing voltage mismatch and completely eliminating the need for complex switch arrays. This unique approach reduces the transistor count by 64 per column ADC, significantly enhancing area efficiency and circuit simplicity. Furthermore, a groundbreaking on-chip fine step range calibration technique is introduced to mitigate the impact of parasitic capacitance, ensuring the precise alignment between coarse and fine steps and achieving exceptional linearity. Fabricated using a 0.18-µm CMOS process, the ADC demonstrates superior performance metrics, including a differential nonlinearity (DNL) of −1/+1.86 LSB, an integral nonlinearity (INL) of −2.74/+2.79 LSB, an effective number of bits (ENOB) of 8.3 bits, and a signal-to-noise and distortion ratio (SNDR) of 51.77 dB. Operating at 240 kS/s with a power consumption of 22.16 µW, the ADC achieves an outstanding figure-of-merit (FOMW) of 0.291 pJ/step. These results demonstrate the proposed architecture’s potential as a transformative solution for high-speed, energy-efficient CIS applications. Full article

In this paper, novel architecture of the true random number generator (TRNG) is presented. The proposed TRNG uses jitter in capacitive oscillators as a source of entropy. These capacitive oscillators exploit the input/output (I/O) buffers of a field-programmable gate array (FPGA) chip. A specific connection between these buffers allows cyclical charging and discharging of a parasitic capacitance associated with an external FPGA pin. If a few pins of an FPGA chip are not connected to any external components, they can be targeted to build the TRNG. The proposed TRNG requires only three external FPGA pins dedicated to capacitive oscillators, as well as 18 look-up tables (LUTs) and 20 flip-flops (FFs). Its throughput amounts to 11–13 Mbit/s. To pass all NIST SP800-22 statistical tests for a wide range of operating temperatures, the TRNG requires a post-processing circuit. The characteristic feature of the proposed TRNG is that it internally generates a signal indicating that a random bit was just produced. Therefore, no external clock signal is needed to sample the output. Full article

In active-matrix organic light-emitting diode (AMOLED) displays, conventional pixel circuits that compensate for the non-uniformity of the threshold voltage (V_T) of low-temperature polycrystalline silicon thin-film transistors (TFTs) can hardly compensate for variations in other TFT parameters, such as carrier mobility (μ₀), subthreshold swing (SS) and the various effects of parasitic capacitance. In recent high-resolution AMOLED displays, as the current required for OLED pixel driving decreases, the current error rate (CER) caused by the non-uniform TFT parameters increases. In this study, we analyzed the influence of each TFT parameter on the CER using SPICE simulation. Based on our analysis, the origin of the increased CER can be classified into two categories: the charging capability of driving TFT and the capacitive coupling effect of the switching TFT. The SS of the driving TFT and the parasitic capacitance of the switching TFT are major factors that affect the CER in terms of the charging capability and capacitive coupling effect, respectively. Our analysis results can be summarized as follows: The SS value of the driving TFT should be high, and its variation should be small to minimize the CER. The variation in the parasitic capacitance of the switching TFT possibly occurs due to long-term bias conditions, as well as process non-uniformity. Therefore, the stability of TFT should also be confirmed for the prevention of anomalous CER caused by long-term bias stress. Full article

The exploitation of high-voltage GaN power switches enables the development of power converters with superior characteristics with respect to components developed with heritage silicon-based technologies. One of the key advantages of GaN switches is their very fast commutation capability due to reduced parasitic capacitance and inductance with respect to silicon devices. The capability of an accurate evaluation of the switch commutations in the design phase is of crucial importance to maximize performance and avoid reliability or electromagnetic compatibility issues in the final converter. In this paper, an accurate evaluation of high-voltage GaN HEMT commutations is performed, exploiting detailed non-linear dynamic models of transistors and electromagnetic simulations of a PCB. A deep insight into the commutation waveforms in the intrinsic device (i.e., conductive drain current and intrinsic node voltages) is proposed to evaluate and explain the mechanisms of almost lossless turn-off and turn-on commutations in a 7 kW DAB converter. The influence on the performance of the PCB parasitics and the driver characteristics are accurately reproduced by simulations, suggesting important guidelines for the optimal design of power converters fully exploiting GaN HEMT’s potential. This detailed simulation/analysis approach for transistor commutation is typically adopted in Radio Frequency amplifier design but also becomes very valuable in power converter design when the very fast commutations of a GaN HEMT at a high switching frequency cannot be fully described and taken under control with conventional approaches used in power electronics design. The simulation results are confirmed by experimental data. Full article

It is shown that the integration of a single-photon avalanche diode (SPAD) together with a BiCMOS gating circuit on one chip reduces the parasitic capacitance a lot and therefore reduces the avalanche build-up time. The capacitance of two bondpads, which are necessary for the connection of an SPAD chip and a gating chip, are eliminated by the integration. The gating voltage transients of the SPAD are measured using an integrated mini-pad and a picoprobe. Furthermore, the gating voltage transients of a CMOS gating circuit and of the BiCMOS gating circuit are compared for the same integrated SPAD. The extension of the 0.35 μm CMOS process by an NPN transistor process module enabled the BiCMOS gating circuit. The avalanche build-up time of the SPAD is reduced to 1.6 ns due to the integration compared to about 3 ns for a wire-bonded off-chip SPAD using the same n+ and p-well as well as the same 0.35 μm technology. Full article

This paper proposes a gallium nitride (GaN)-based very-high-frequency (VHF) resonant flyback converter with integrated magnetics, which utilizes the parasitic inductance and capacitance to reduce the passive components count and volume of the converter. Both the primary leakage inductance and the secondary leakage inductance of the transformer are utilized as the resonance inductor, while the parasitic capacitance of the power devices is utilized as the resonance capacitor. An analytical circuit model is proposed to determine the electrical parameters of the transformer so as to achieve zero voltage switching (ZVS) and zero current switching (ZCS). Furthermore, an air-core transformer was designed using the improved Wheeler’s formula, and finite element analyses were carried out to fine-tune the structure to achieve the accurate design of the electrical parameters. Finally, a 30 MHz, 15 W VHF resonant flyback converter prototype is built with an efficiency of 83.1% for the rated power. Full article

In order to reduce the influence of coupling capacitance variations on cable voltage measurement, this paper proposes a self-compensating non-intrusive ring-type AC voltage sensor based on capacitive coupling. A theoretical model of the sensor was established, and the influence of parasitic capacitance changes on sensor output was analyzed. Furthermore, a theoretical analysis shows that the parasitic capacitance between the external cable and the sensing probe, as well as between the ground and the sensing probe, will significantly affect the sensitivity of the sensor and increases the measurement error. A ring-type inductive probe and a signal processing circuit were designed, incorporating a reference signal to compensate for the influence of coupling capacitance variations. Additionally, to minimize the impact of parasitic capacitance on sensor output, the length of the outer ring electrode was extended, and a PTFE housing was designed for protection. A prototype of the sensor was developed and tested. This prototype has a good linear response to AC voltage in the measurement range of 0–1000 V with a linearity of 0.86%. The effects of changes in cable diameter and cable position on the measurement were tested separately. The worst-case error of the sensor output is less than 6.44%, representing a reduction of 21.4% compared to the uncompensated case. Under external cable interference, the sensor exhibited an output error of less than 1.85%. The results show that the designed sensor can accurately measure cable voltage despite changes in cable diameter or installation position, and also demonstrates effective shielding against external interference. Full article

This paper introduces a novel differential combiner designed to effectively address parasitic capacitances of transistors used in power amplifier (PA) designs with precise compensation at a specified frequency. The combiner consists of a λ/4 transmission line with an integrated capacitor of value 2COUT at its midpoint, which ensures accurate cancellation of parasitic effects. This design connects the drain pins of two transistors, which are considered identical in this configuration. By eliminating the need for complex parasitic compensation techniques, this method significantly simplifies the design process of Doherty Power Amplifiers (DPAs). Extensive simulations validate the effectiveness of this approach, highlighting its potential as a versatile and straightforward solution for next-generation communication systems. Full article

Wide bandgap (WBG) power semiconductor devices are increasingly replacing silicon IGBTs in high-power and high-voltage power electronics applications. However, there is a significant gap in the literature regarding efficient testing methodologies for high-power and high-voltage converters under constrained laboratory resources. This paper addresses this gap by presenting comprehensive, hardware-focused testing methodologies for high-power and high-voltage WBG power semiconductor-based converter bring-up before the control validation phase steps in. The proposed methods enable thorough evaluation and validation of converter hardware, including device switching characteristics, driving circuit functionality, thermal management performance, insulation integrity, and sustained operation at full power. We utilized the double pulse test (DPT) to characterize switching performance in a two-level phase leg configuration, extract circuit parasitics, and validate magnetic components. The DPT was further applied to optimize gate driving circuits, validate overcurrent protection mechanisms, and measure device on-resistance. Additionally, a multicycle test was introduced to rapidly assess steady-state converter performance and estimate efficiency. Recognizing the critical role of thermal management in high-power converters, our methodologies extend to the experimental extraction of key thermal parameters—such as junction-to-ambient thermal resistance and thermal capacitance—via a heat loss injection method. A correlation method between temperature sensor measurements and junction temperature is presented to enhance the accuracy of device temperature monitoring during tests. To ensure reliability and safety, dielectric withstand tests and partial discharge measurements were conducted at both component and converter levels under conventional 60 Hz sinusoidal and high-frequency PWM waveforms. Finally, we highlight the importance of testing converters under full voltage, current, and thermal conditions through power circulating tests with minimal power consumption, applicable to both non-isolated and isolated high-power converters. Practical examples are provided to demonstrate the effectiveness and applicability of these hardware testing methodologies. Full article

This study investigates a hybrid microelectromechanical system (MEMS) acoustic resonator through a hybrid approach to combine capacitive and piezoelectric transduction mechanisms, thus harnessing the advantages of both transducer technologies within a single device. By seamlessly integrating both piezoelectric and capacitive transducers, the newly designed hybrid resonators mitigate the limitations of capacitive and piezoelectric resonators. The unique hybrid configuration holds promise to significantly enhance overall device performance, particularly in terms of quality factor (Q-factor), insertion loss, and motional impedance. Moreover, the dual-transduction approach improves the signal-to-noise ratio and reduces feedthrough noise levels at higher frequencies. In this paper, the detailed design, complex fabrication processes, and thorough experimental validation are presented, demonstrating substantial performance enhancement potentials. A hybrid disk resonator with a single side-supporting anchor achieved an outstanding loaded Q-factor higher than 28,000 when operating under a capacitive drive and piezoelectric sense configuration. This is comparably higher than the measured Q-factor of 7600 for another disk resonator with two side-supporting anchors. The hybrid resonator exhibits a high Q-factor at its resonance frequency at 20 MHz, representing 2-fold improvement over the highest reported Q-factor for similar MEMS resonators in the literature. Also, the dual-transduction approach resulted in a more than 30 dB improvement in feedthrough suppression for devices with a 500 nm-thick ZnO layer, while hybrid resonators with a thicker piezoelectric layer of 1300 nm realized an even greater feedthrough suppression of more than 50 dB. The hybrid resonator integration strategy discussed offers an innovative solution for current and future advanced RF front-end applications, providing a versatile platform for future innovations in on-chip resonator technology. This work has the potential to lead to advancements in MEMS resonator technology, facilitating some significant improvements in multi-frequency and frequency agile RF applications through the original designs equipped with integrated capacitive and piezoelectric transduction mechanisms. The hybrid design also results in remarkable performance metrics, making it an ideal candidate for integrating next-generation wireless communication devices where size, cost, and energy efficiency are critical. Full article

This study investigates the operational characteristics of AlGaN/GaN high-electron-mobility transistors (HEMTs) by employing various passivation materials with different dielectric constants and passivation structures. To ensure the simulation reliability, the parameters were calibrated based on the measured data from the fabricated basic Si₃N₄ passivation structure of the HEMT. The Si₃N₄ passivation material was replaced with high-k materials, such as Al₂O₃ and HfO₂, to improve the breakdown voltage. The Al₂O₃ and HfO₂ passivation structures achieved breakdown voltage improvements of 6.62% and 17.45%, respectively, compared to the basic Si₃N₄ passivation structure. However, the increased parasitic capacitances reduced the cut-off frequency. To mitigate this reduction, the operational characteristics of hybrid and partial passivation structures were analyzed. Compared with the HfO₂ passivation structure, the HfO₂ partial passivation structure exhibited a 7.6% reduction in breakdown voltage but a substantial 82.76% increase in cut-off frequency. In addition, the HfO₂ partial passivation structure exhibited the highest Johnson’s figure of merit. Consequently, considering the trade-off relationship between breakdown voltage and frequency characteristics, the HfO₂ partial passivation structure emerged as a promising candidate for high-power and high-frequency AlGaN/GaN HEMT applications. Full article

A direct bidirectional current discharge path between the input/output (I/O) and ground (GND) is essential for the robust protection of charging device models (CDM) in the tightly constrained design parameters of advanced low-voltage (LV) processes. Dual-direction silicon controlled rectifiers (DDSCRs) serve as ESD protection devices with high efficiency unit area discharge, enabling bidirectional electrostatic protection. However, the high trigger voltage of conventional DDSCR makes it unsuitable for ASICs used for the preamplification of biomedical signals, which only operate at low supply voltage. To address this issue, a self-biased triggered DDSCR (STDDSCR) structure is proposed to further reduce the trigger voltage. When the ESD pulse comes, the external RC trigger circuit controls the PMOS turn-on by self-bias, and the current release path is opened in advance to reduce the trigger voltage. As the ESD pulse voltage increases, the SCR loop opens to establish positive feedback and drain the amplified current. Additionally, the junction capacitance is decreased through high-resistance epitaxy and low-concentration P-well injection to further lower the trigger voltage. The simulation results of LTspice and TCAD respectively demonstrate that ESD devices can clamp transient high voltages earlier, with low parasitic capacitance and leakage current suitable for ESD protection of high-speed ports up to 1.5 V under normal operating conditions. Full article

Planar magnetic components have been widely used in high-density power converters and are suitable for various topologies. The application of planar inductors in LLC resonant converters can lead to parasitic capacitance, which causes current ringing and results in EMI issues. To mitigate the impact of current ringing, the parasitic capacitance of the planar inductor needs to be reduced. This paper proposes a new six-turn interleaved winding design. Compared to the previous four-turn interleaved winding design, it maintains low parasitic capacitance while positioning both the input and output terminals of the inductor on the outer turn, further enhancing the integration of high-density power converters. The parasitic capacitance was calculated using theoretical methods and verified through finite element simulations. Experimental validation was conducted using an LLC resonant converter test platform. Compared to the previous four-turn interleaved winding design, the new six-turn interleaved winding design satisfies both the input and output terminals, using an outer turn configuration. Additionally, the new design exhibits reduced parasitic capacitance and is suitable for use in LLC resonant converters, where it also minimizes current ringing. Full article

This study employs an innovative dynamic switching test system to investigate the dynamic switching characteristics of three p-GaN HEMT devices. The dynamic switching characteristics are different from the previous research on the dynamic resistance characteristics of GaN devices, and the stability of GaN devices can be analyzed from the perspective of switching characteristics. Based on the theory of dynamic changes in threshold opening voltage and capacitance caused by electrical stress, the mechanism of dynamic switching characteristics of GaN HEMT devices is studied and analyzed in detail. The test results have shown that electrical stress induces trap ionization within the device, resulting in fluctuations in electric potential and ultimately leading to alterations in two critical factors of the dynamic switching characteristics of GaN HEMT devices, the parasitic capacitance and the threshold voltage. The dynamic changes in capacitance before and after electrical stress vary among devices, resulting in different dynamic switching characteristics. The test system is capable of extracting the switching waveform for visual comparison and quantitatively calculating the changes in switching parameters before and after electrical stressing. This test provides a prediction for the drift of switch parameters, offering pre-guidance for the robustness of the optimized application scheme. Full article