Power optimization of core-based systems by address bus encoding L Benini, G De Micheli, E Macii, M Poncino, S Quer IEEE Transactions on Very Large Scale Integration (VLSI) Systems 6 (4), 554-562, 1998 | 143 | 1998 |
System-level power optimization of special purpose applications: The beach solution L Benini, G De Micheli, E Macii, M Poncino, S Quer Proceedings of the 1997 international symposium on Low power electronics and …, 1997 | 137 | 1997 |
Improved reachability analysis of large finite state machines G Cabodi, P Camurati, S Quer Proceedings of International Conference on Computer Aided Design, 354-360, 1996 | 123 | 1996 |
A smart meter infrastructure for smart grid IoT applications M Orlando, A Estebsari, E Pons, M Pau, S Quer, M Poncino, L Bottaccioli, ... IEEE Internet of Things Journal 9 (14), 12529-12541, 2021 | 108 | 2021 |
Disjunctive partitioning and partial iterative squaring: An effective approach for symbolic traversal of large circuits G Cabodi, P Camurati, L Lavagno, S Quer Proceedings of the 34th annual Design Automation Conference, 728-733, 1997 | 101 | 1997 |
Improving SAT-based bounded model checking by means of BDD-based approximate traversals G Cabodi, S Nocco, S Quer 2003 Design, Automation and Test in Europe Conference and Exhibition, 898-903, 2003 | 89 | 2003 |
A densely-deployed, high sampling rate, open-source air pollution monitoring WSN B Montrucchio, E Giusto, MG Vakili, S Quer, R Ferrero, C Fornaro IEEE Transactions on Vehicular Technology 69 (12), 15786-15799, 2020 | 60 | 2020 |
Can BDDs compete with SAT solvers on bounded model checking? G Cabodi, P Camurati, S Quer Proceedings of the 39th annual Design Automation Conference, 117-122, 2002 | 49 | 2002 |
Improving the efficiency of BDD-based operators by means of partitioning G Cabodi, P Camurati, S Quer IEEE transactions on computer-aided design of integrated circuits and …, 1999 | 42 | 1999 |
Symbolic exploration of large circuits with enhanced forward/backward traversals. G Cabodi, P Camurati, S Quer EURO-DAC 94, 22-27, 1994 | 37 | 1994 |
Hardware model checking competition 2014: an analysis and comparison of model checkers and benchmarks G Cabodi, C Loiacono, M Palena, P Pasini, D Patti, S Quer, ... Journal on Satisfiability, Boolean Modeling and Computation 9 (1), 135-172, 2014 | 35 | 2014 |
Stepping forward with interpolants in unbounded model checking G Cabodi, M Murciano, S Nocco, S Quer Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006 | 33 | 2006 |
Cycle-based symbolic simulation of gate-level synchronous circuits V Bertacco, M Damiani, S Quer Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 391-396, 1999 | 31 | 1999 |
Efficient state space pruning in symbolic backward traversal G Cabodi, P Camurati, S Quer Proceedings 1994 IEEE International Conference on Computer Design: VLSI in …, 1994 | 31 | 1994 |
Strengthening model checking techniques with inductive invariants G Cabodi, S Nocco, S Quer IEEE transactions on computer-aided design of integrated circuits and …, 2008 | 28 | 2008 |
Benchmarking a model checker for algorithmic improvements and tuning for performance G Cabodi, S Nocco, S Quer Formal Methods in System Design 39, 205-227, 2011 | 25 | 2011 |
Mixing forward and backward traversals in guided-prioritized BDD-based verification G Cabodi, S Nocco, S Quer Computer Aided Verification: 14th International Conference, CAV 2002 …, 2002 | 23 | 2002 |
Speeding up model checking by exploiting explicit and hidden verification constraints G Cabodi, P Camurati, L Garcia, M Murciano, S Nocco, S Quer 2009 Design, Automation & Test in Europe Conference & Exhibition, 1686-1691, 2009 | 22 | 2009 |
Boosting interpolation with dynamic localized abstraction and redundancy removal G Cabodi, M Murciano, S Nocco, S Quer ACM Transactions on Design Automation of Electronic Systems (TODAES) 13 (1 …, 2008 | 19 | 2008 |
Full symbolic ATPG for large circuits G Cabodi, P Camurati, S Quer Proceedings., International Test Conference, 980-988, 1995 | 19 | 1995 |