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A two-level particle swarm optimization: profiling and software/hardware implementation
Particle swarm optimization (PSO), a population-based stochastic method, was developed to address difficult optimization issues like the flexible job...
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Hardware implementation of digital pseudo-random number generators for real-time applications
This paper introduces the hardware implementation of Digital Pseudo-Random Number Generators (DPRNG) based on chaotic systems. First,...
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Hardware architecture and memristor-crossbar implementation of type-2 fuzzy system with type reduction and in-situ training
The Type-2 fuzzy set is a fuzzy set with fuzzy membership degrees. This set is used when accurately determining the membership degree of a fuzzy set...
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GSGP-hardware: instantaneous symbolic regression with an FPGA implementation of geometric semantic genetic programming
Geometric Semantic Genetic Programming (GSGP) proposed an important enhancement to GP-based learning, incorporating search operators that operate...
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Hardware implementation of iterative method for enhanced affine motion estimation in Versatile video coding
Versatile Video Coding (VVC), the latest advancement in video coding standards, significantly outperforms its predecessor, High Efficiency Video...
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Hardware implementation of SLAM algorithms: a survey on implementation approaches and platforms
Simultaneous localization and mapping (SLAM) is an active research topic in machine vision and robotics. It has various applications in many...
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In-depth Correlation Power Analysis Attacks on a Hardware Implementation of CRYSTALS-Dilithium
During the standardisation process of post-quantum cryptography, NIST encourages research on side-channel analysis for candidate schemes. As the...
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Real-time lossless image compression by dynamic Huffman coding hardware implementation
Over the decades, implementing information technology (IT) has become increasingly common, equating to an increasing amount of data that needs to be...
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Design and implementation of hardware-efficient architecture for saturation-based image dehazing algorithm
For real-time single-image dehazing, this paper suggests a straightforward and efficient saturation-based transmission map estimation method. For the...
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Differential fault analysis attack-tolerant hardware implementation of AES
Cryptographic circuits contain various confidential information and are susceptible to fraudulent manipulations, commonly called attacks, performed...
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Hardware implementation of particle swarm optimization with chaotic fractional-order
Engineering optimization methods based on meta-heuristic algorithms are computationally demanding and might present complex implementation issues for...
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A hardware-friendly logarithmic quantization method for CNNs and FPGA implementation
Convolutional Neural Networks (CNNs) have been widely used in various fields due to their high accuracy and efficiency. The performance of CNNs is...
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FPGA implementation of hardware accelerated RTOS based on real-time event handling
Actual trends in the real-time system field consists of migration towards complex central processing unit (CPU) architectures with enhanced execution...
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Robust hardware implementation of a block-cipher scheme based on chaos and biological algebraic operations
Currently, chaos-based cryptosystems are widely used for the reason of protecting sensitive data. Various different chaos-based cryptography systems...
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Method for Convolutional Neural Network Hardware Implementation Based on a Residue Number System
AbstractConvolutional Neural Networks (CNN) show high accuracy in pattern recognition solving problem but have high computational complexity, which...
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Fast and Efficient Hardware Implementation of HQC
This work presents a hardware design for constant-time implementation of the HQC (Hamming Quasi-Cyclic) code-based key encapsulation mechanism. HQC...
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2D hyperchaotic Styblinski-Tang map for image encryption and its hardware implementation
A novel 2D chaotic system is presented, which is inspired by Styblinski Tang (ST) function employed as optimization test function. It is a challenge...
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Hardware implementation and validation of the fast variable block size motion estimation architecture for HEVC Standard
High-Efficiency Video Coding (HEVC) has become popular according to its excellent coding performance, in particular in the case of high-resolution...
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An Efficient Hardware Implementation of Crystal-Dilithium on FPGA
Crystal-Dilithium is a post-quantum signature scheme and has earned recognition as one of NIST’s selected digital signature standards. Compared with...
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Real-time hardware architecture of an ECG compression algorithm for IoT health care systems and its VLSI implementation
The Internet of Things (IoT) in the medical and biomedical field proposes new and efficient hardware for healthcare services. Thanks to...
