Pengguna:Dare2Leap/Bak pasir 3

Layout for the silicon implementation of a six transistor SRAM memory cell.

Sel memori adalah dasar pembangun memori komputer. Sel memori adalah sirkuit elektronik yang menyimpan sebuah bit informasi biner dan harus disetel untuk menyimpan bit 1 logika (level tegangan tinggi) dan disetel ulang untuk menyimpan bit 0 logika (level tegangan rendah). Nilainya dijaga/disimpan sampai diubah oleh proses setel/setel ulang. Nilai dalam sel memori dapat diakses dengan membacanya.

Dalam sejarah komputasi, berbagai arsitektur memori sel digunakan, termasuk memori inti dan memori gelembung. Sekarang, arsitektur sel memori yang paling umum adalah memori MOS, yang terdiri atas sel memori semikonduktor logam-oksida. Memori akses acak (RAM) menggunakan transistor efek-medan MOS (MOSFET) sebagai flip-flop dan kapasitor MOS untuk beberapa jenis RAM.

Sel memori SRAM (RAM statik) adalah jenis sirkuit flip-flop, yang biasanya diterapkan menggunakan MOSFET. Mereka menggunakan daya yang sangat rendah untuk menjaga nilai yang disimpan ketika tidak diakses. Jenis kedua, DRAM (RAM dinamis) berbasis kapasitor MOS. Mengisi dan menghabiskan kapasitor bisa menyimpan '1' atau '0' dalam sel. Namun, listrik dalam kapasitor ini akan bocor perlahan-lahan, dan harus disegarkan secara berkala. Karena proses penyegaran ini, DRAM menggunakan lebih banyak daya. Namun, DRAM bisa menyimpan lebih banyak data dalam suatu area.

Pada sisi lain, sebagian besar memori non-volatil (NVM) berbasis arsitektur sel memori gerbang mengambang. Teknologi memori non-volatil, seperti EPROM, EEPROM, dan memori flash menggunakan sel memori gerbang mengambang, yang berbasis transistor MOSFET gerbang mengambang.

Deskripsi

Sel memori adalah dasar pembangun memori. Ini bisa diterapkan menggunakan beberapa teknologi, seperti dwikutub, MOS, dan perangkat semikonduktor lain. Sel memori juga bisa dibuat dari bahan magnetik seperti inti ferrit atau gelembung magnetik. Kegunaan sel memori biner, dengan teknologi apapun, selalu sama. Sel memori menyimpan satu bit informasi biner yang bisa diakses dengan membaca selnya dan harus disetel untuk menyimpan 1 dan direset untuk menyimpan 0.

Signifikansi

Square array of DRAM memory cells being read

Sirkuit logika tanpa sel memori atau jalur masukan adalah sirkuit kombinasional. Nilai outputnya hanya bergantung pada nilai inputnya saat ini. Mereka tidak memiliki memori. Namun, memori adalah salah satu elemen utama sistem digital. Dalam komputer, memori memungkinkan penyimpanan program dan data secar bersamaan dan sel memori juga digunakan untuk penyimpanan sementara output sirkuit kombinasional untuk nanti digunakan oleh sistem digital. Sirkuit logika yang menggunakan sel memori adalah sirkuit sekuensial. Outputnya tidak hanya bergantung pada nilai inputnya saat ini, tetapi juga bergantung pada keadaan sirkuit sebelumnya, yang ditentukan oleh nilai yang disimpan pada sel memorinya. Sirkuit tersebut membutuhkan generator waktu atau jam untuk operasinya.

Logic circuits without memory cells or feedback paths are called combinational, their outputs values depend only on the current value of their input values. They do not have memory. But memory is a key element of digital systems. In computers, it allows to store both programs and data and memory cells are also used for temporary storage of the output of combinational circuits to be used later by digital systems. Logic circuits that use memory cells are called sequential circuits. Its output depends not only on the present value of its inputs, but also on the circuits previous state, as determined by the values stored on its memory cells. These circuits require a timing generator or clock for their operation.

Saat ini, sebagian besar memori komputer yang digunakan dalam sistem komputer menggunakan sel DRAM; karena susunannya lebih kecil daripada SRAM, memori bisa dibuat lebih padat. Ini berujung pada memori yang lebih murah dengan kapasitas yang lebih besar. Karena sel memori DRAM menyimpan nilainya sebagai muatan kapasitor, dan ada masalah kebocoran, nilainya harus ditulis secara terus menerus. Ini adalah salah satu penyebab sel DRAM lebih lambat daripada sel SRAM (RAM statik) yang lebih besar, yang nilainya selalu tersedia. Oleh karena itu, memori SRAM digunakan untuk cache dalam chip dalam chip mikroprosesor modern.

Computer memory used in most contemporary computer systems is built mainly out of DRAM cells; since the layout is much smaller than SRAM, it can be more densely packed yielding cheaper memory with greater capacity. Since the DRAM memory cell stores its value as the charge of a capacitor, and there are current leakage issues, its value must be constantly rewritten. This is one of the reasons that make DRAM cells slower than the larger SRAM (static RAM) cells, which has its value always available. That is the reason why SRAM memory is used for on-chip cache included in modern microprocessor chips.

Sejarah

Informasi lebih lanjut: Memori komputer § Sejarah

Pada 11 Desember 1946, Freedie Williams mengajukan paten untuk perangkat penyimpanan tabung sinar katode (CRT) (tabung Williams) dengan 128 kata 40-bit. Itu beroperasi pada 1947 dan merupakan implementasi praktis pertama memori akses acak (RAM). Pada tahun itu, paten pertama untuk memori inti magnetik diajukan oleh Frederick Viehe. Memori inti magnetik yang praktis dikembangkan oleh An Wang pada 1948, dan diperbaiki oleh Jay Forrester dan Jan A. Rajchman pada awal 1950-an, sebelum dikomersialkan oleh komputer Whirlwind pada 1953. Ken Olsen juga berkontribusi ke pengembangannya.

32x32 core memory plane storing 1024 bits of data.

On December 11, 1946 Freddie Williams applied for a patent on his cathode-ray tube (CRT) storing device (Williams tube) with 128 40-bit words. It was operational in 1947 and is considered the first practical implementation of random-access memory (RAM). In that year, the first patent applications for magnetic-core memory were filed by Frederick Viehe. Practical magnetic-core memory was developed by An Wang in 1948, and improved by Jay Forrester and Jan A. Rajchman in the early 1950s, before being commercialised with the Whirlwind computer in 1953. Ken Olsen also contributed to its development.

Memori semikonduktor dikembangkan pada awal 1960-an dengan sel memori bipolar, yang terdiri dari transistor bipolar. Walaupun lebih cepat,memori semikonduktor tidak bisa bersaing dengan memori inti magnetik yang lebih murah.

Semiconductor memory began in the early 1960s with bipolar memory cells, made of bipolar transistors. While it improved performance, it could not compete with the lower price of magnetic-core memory.

MOS memory cells

Informasi lebih lanjut: Memori MOS dan Memori akses acak § Sejarah

Intel 1103, a 1970 metal-oxide-semiconductor (MOS) dynamic random-access memory (DRAM) chip.

Penemuan MOSFET (transistor efek-medan semikonduktor logam-oksida), juga dikenal sebagai transistor MOS, oleh Mohamed M. Atalla dan Dawon Kahng pada Bell Labs pada 1959, memungkinkan penggunaan praktis transistor semikonduktor logam-oksida sebagai elemen penyimpanan sel memori, sebuah fungsi yang sebelumnya disediakan oleh inti-inti magnetik. Sel memori modern pertama diperkenalkan pada 1964, ketika John Schmidt mendesain memori akses acak statik (SRAM) MOS p-channel (PMOS) 64-bit pertama.

The invention of the MOSFET (metal-oxide-semiconductor field-effect transistor), also known as the MOS transistor, by Mohamed M. Atalla and Dawon Kahng at Bell Labs in 1959, enabled the practical use of metal–oxide–semiconductor (MOS) transistors as memory cell storage elements, a function previously served by magnetic cores. The first modern memory cells were introduced in 1964, when John Schmidt designed the first 64-bit p-channel MOS (PMOS) static random-access memory (SRAM).

SRAM typically has six-transistor cells, whereas DRAM (dynamic random-access memory) typically has single-transistor cells. In 1965, Toshiba's Toscal BC-1411 electronic calculator used a form of capacitive bipolar DRAM, storing 180-bit data on discrete memory cells, consisting of germanium bipolar transistors and capacitors. MOS technology is the basis for modern DRAM. In 1966, Dr. Robert H. Dennard at the IBM Thomas J. Watson Research Center was working on MOS memory. While examining the characteristics of MOS technology, he found it was capable of building capacitors, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of a single-transistor DRAM memory cell. In 1967, Dennard filed a patent for a single-transistor DRAM memory cell, based on MOS technology.

The first commercial bipolar 64-bit SRAM was released by Intel in 1969 with the 3101 Schottky TTL. One year later, it released the first DRAM integrated circuit chip, the Intel 1103, based on MOS technology. By 1972, it beat previous records in semiconductor memory sales. DRAM chips during the early 1970s had three-transistor cells, before single-transistor cells became standard since the mid-1970s.

CMOS memory was commercialized by RCA, which launched a 288-bit CMOS SRAM memory chip in 1968. CMOS memory was initially slower than NMOS memory, which was more widely used by computers in the 1970s. In 1978, Hitachi introduced the twin-well CMOS process, with its HM6147 (4 kb SRAM) memory chip, manufactured with a 3 µm process. The HM6147 chip was able to match the performance of the fastest NMOS memory chip at the time, while the HM6147 also consumed significantly less power. With comparable performance and much less power consumption, the twin-well CMOS process eventually overtook NMOS as the most common semiconductor manufacturing process for computer memory in the 1980s.

The two most common types of DRAM memory cells since the 1980s have been trench-capacitor cells and stacked-capacitor cells. Trench-capacitor cells are where holes (trenches) are made in a silicon substrate, whose side walls are used as a memory cell, whereas stacked-capacitor cells are the earliest form of three-dimensional memory (3D memory), where memory cells are stacked vertically in a three-dimensional cell structure. Both debuted in 1984, when Hitachi introduced trench-capacitor memory and Fujitsu introduced stacked-capacitor memory.

Floating-gate MOS memory cells

Lihat pula: Floating-gate MOSFET dan Nonvolatile memory

The floating-gate MOSFET (FGMOS) was invented by Dawon Kahng and Simon Sze at Bell Labs in 1967. They proposed the concept of floating-gate memory cells, using FGMOS transistors, which could be used to produce reprogrammable ROM (read-only memory). Floating-gate memory cells later became the basis for non-volatile memory (NVM) technologies including EPROM (erasable programmable ROM), EEPROM (electrically erasable programmable ROM) and flash memory.

Flash memory was invented by Fujio Masuoka at Toshiba in 1980. Masuoka and his colleagues presented the invention of NOR flash in 1984, and then NAND flash in 1987. Multi-level cell (MLC) flash memory was introduced by NEC, which demonstrated quad-level cells in a 64 Mb flash chip storing 2-bit per cell in 1996. 3D V-NAND, where flash memory cells are stacked vertically using 3D charge trap flash (CTP) technology, was first announced by Toshiba in 2007, and first commercially manufactured by Samsung Electronics in 2013.

Implementation

The following schematics detail the three most used implementations for memory cells :

• The dynamic random access memory cell (DRAM)
• The static random access memory cell (SRAM)
• Flip-flops like the J/K shown below.

DRAM cell (1 transistor and one capacitor)

SRAM cell (6 transistors)

Clocked J/K flip-flop

Operation

DRAM memory cell

Die of the MT4C1024 (1994) integrating one-mebibit of DRAM memory cells.

Storage

The storage element of the DRAM memory cell is the capacitor labeled (4) in the diagram above. The charge stored in the capacitor degrades over time, so its value must be refreshed (read and rewritten) periodically. The nMOS transistor (3) acts as a gate to allow reading or writing when open or storing when closed.

Reading

For reading the Word line (2) drives a logic 1 (voltage high) into the gate of the nMOS transistor (3) which makes it conductive and the charge stored at the capacitor (4) is then transferred to the bit line (1). The bit line will have a parasitic capacitance (5) that will drain part of the charge and slow the reading process. The capacitance of the bit line will determine the needed size of the storage capacitor (4). It is a trade-off. If the storage capacitor is too small, the voltage of the bit line would take too much time to raise or not even rise above the threshold needed by the amplifiers at the end of the bit line. Since the reading process degrades the charge in the storage capacitor (4) its value is rewritten after each read.

Writing

The writing process is the easiest, the desired value logic 1 (high voltage) or logic 0 (low voltage) is driven into the bit line. The word line activates the nMOS transistor (3) connecting it to the storage capacitor (4). The only issue is to keep it open enough time to ensure that the capacitor is fully charged or discharged before turning off the nMOS transistor (3).

SRAM memory cell

SRAM memory cell depicting Inverter Loop as gates

An animated SR latch. Black and white mean logical '1' and '0', respectively.
(A) S = 1, R = 0: set
(B) S = 0, R = 0: hold
(C) S = 0, R = 1: reset
(D) S = 1, R = 1: not allowed
Transitioning from the restricted combination (D) to (A) leads to an unstable state.

Storage

The working principle of SRAM memory cell can be easier to understand if the transistors M1 through M4 are drawn as logic gates. That way it is clear that at its heart, the cell storage is built by using two cross-coupled inverters. This simple loop creates a bi-stable circuit. A logic 1 at the input of the first inverter turns into a 0 at its output, and it is fed into the second inverter which transforms that logic 0 back to a logic 1 feeding back the same value to the input of the first inverter. That creates a stable state that does not change over time. Similarly the other stable state of the circuit is to have a logic 0 at the input of the first inverter. After been inverted twice it will also feedback the same value.

Therefore there are only two stable states that the circuit can be in:

• $\scriptstyle Q$ = 0 and   $\scriptstyle {\overline {Q}}$ = 1
• $\scriptstyle Q$ = 1 and   $\scriptstyle {\overline {Q}}$ = 0

Reading

To read the contents of the memory cell stored in the loop, the transistors M5 and M6 must be turned on. when they receive voltage to their gates from the word line ($\scriptstyle WL$), they become conductive and so the $\scriptstyle Q$ and  $\scriptstyle {\overline {Q}}$  values get transmitted to the bit line ($\scriptstyle BL$) and to its complement ($\scriptstyle {\overline {BL}}$). Finally this values get amplified at the end of the bit lines.

Writing

The writing process is similar, the difference is that now the new value that will be stored in the memory cell is driven into the bit line ($\scriptstyle BL$) and the inverted one into its complement ($\scriptstyle {\overline {BL}}$). Next transistors M5 and M6 are open by driving a logic one (voltage high) into the word line ($\scriptstyle WL$). This effectively connects the bit lines to the by-stable inverter loop. There are two possible cases:

1. If the value of the loop is the same as the new value driven, there is no change.
2. If the value of the loop is different from the new value driven there are two conflicting values, in order for the voltage in the bit lines to overwrite the output of the inverters, the size of the M5 and M6 transistors must be larger than that of the M1-M4 transistors. This allows more current to flow through first ones and therefore tips the voltage in the direction of the new value, at some point the loop will then amplify this intermediate value to full rail.

Flip-flop

Artikel utama: Flip-flop (electronics)

The flip-flop has many different implementations, its storage element is usually a latch consisting of a NAND gate loop or a NOR gate loop with additional gates used to implement clocking. Its value is always available for reading as an output. The value remains stored until it is changed through the set or reset process. Flip-flops are typically implemented using MOSFET transistors.

Floating gate

A flash memory cell

Lihat pula: Floating-gate MOSFET dan Charge trap flash

Floating-gate memory cells, based on floating-gate MOSFET transistors, are used for most non-volatile memory (NVM) technologies, including EPROM, EEPROM and flash memory. According to R. Bez and A. Pirovano:

A floating-gate memory cell is basically an MOS transistor with a gate completely surrounded by dielectrics (Fig. 1.2), the floating-gate (FG), and electrically governed by a capacitive-coupled control-gate (CG). Being electrically isolated, the FG acts as the storing electrode for the cell device. Charge injected into the FG is maintained there, allowing modulation of the ‘apparent’ threshold voltage (i.e. VT seen from the CG) of the cell transistor.

See also

• Dynamic random-access memory
• Flip-flop (electronics)
• Row hammer
• Static random-access memory