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Issues list

`define alignment formatter Verilog code formatter issues
#2034 opened Oct 30, 2023 by PaperL
1
define is not properly considering formatter Verilog code formatter issues preprocessor anything related to preprocessing (conditionals, macros, etc.)
#2033 opened Oct 28, 2023 by justincdas
1
verible-verilog-obfuscate fails to obfuscate 'sample' keyword in struct bug Something isn't working
#2032 opened Oct 27, 2023 by tictacmenthe
1
Formatting failed to converge when three or more comment lines before else formatter Verilog code formatter issues
#2028 opened Oct 19, 2023 by ASintzoff
format does not work for import package when placed at module header inside an ifdef formatter Verilog code formatter issues
#2027 opened Oct 17, 2023 by prokie
Parsing error in formatter bug Something isn't working formatter Verilog code formatter issues
#2025 opened Oct 11, 2023 by ASintzoff
1
Build without Bazel build system matters pertaining to building Verible
#2023 opened Oct 10, 2023 by the-moog
4
Attempting to use the "type operator" results in a syntax error. rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2022 opened Oct 3, 2023 by fpgauserdude
Assign alignment breaks when line length would go over column limit formatter Verilog code formatter issues
#2021 opened Sep 29, 2023 by shareefj
1
issue with installation
#2018 opened Sep 26, 2023 by gauthamsaiv
1
Declaring Nets with Certain Explicit Data Types Results in Error rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2015 opened Sep 20, 2023 by bkueffle
1
parser cannot accept macro in the port map rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2010 opened Sep 5, 2023 by fpgauserdude
Wire is not seen as kind (like var) but as type formatter Verilog code formatter issues
#2009 opened Sep 1, 2023 by aavdiere
Check failure when using signed wires formatter Verilog code formatter issues rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2008 opened Aug 31, 2023 by aquohn
Enhance SyntaxTreeRule testing by pointing to syntax errors when present enhancement New feature or request style-linter Verilog style-linter issues testing matters pertaining to unit-tests, integration-tests, continuous/presubmit testing
#2007 opened Aug 30, 2023 by IEncinas10
A problem with syntax tool's python wrapper
#2006 opened Aug 30, 2023 by pinkcatfly
1
Would you consider opening up the interface for calls?
#2005 opened Aug 25, 2023 by 17Reset
Support disabling *all* linting rules? enhancement New feature or request style-linter Verilog style-linter issues
#2004 opened Aug 24, 2023 by mithro
3
Is there a way to make the right parenthesis aligned in instantiations ? formatter Verilog code formatter issues
#2003 opened Aug 21, 2023 by MahmoudKMaarouf
1
Logic declarations not formatted like ports , even with same align settings formatter Verilog code formatter issues
#2002 opened Aug 21, 2023 by MahmoudKMaarouf
let statement not properly formatted formatter Verilog code formatter issues
#2001 opened Aug 17, 2023 by corco
1
Developing custom verible linting rules for my organization? style-linter Verilog style-linter issues
#1999 opened Aug 14, 2023 by Lightborne
4
Consider distributing via Open Build Service
#1998 opened Aug 14, 2023 by siddhpant
Documentation: show how to create a compilation database with bazel documentation Improvements or additions to documentation
#1996 opened Aug 10, 2023 by IEncinas10
request switch to turn off preprocessor in verible-verilog-syntax rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#1995 opened Aug 10, 2023 by fpgauserdude
2
ProTip! Exclude everything labeled bug with -label:bug.