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{{short description|32-bit ARM core}}
{{list-cleanup|date=November 2015}}
{{cleanup list|date=November 2015}}
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{{Infobox CPU
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'''ARM11''' is a group of older [[32-bit]] [[reduced instruction set computer|RISC]] [[ARM architecture|ARM]] processor cores licensed by [[ARM Holdings]].<ref name="ARM11-Web">[https://www.arm.com/products/processors/classic/arm11/index.php ARM11 Family Webpage; ARM Holdings.]</ref> The cores were released from 2002 to 2005 and consisted of ARM1136J(F)-S, ARM1156T2(F)-S, ARM1176JZ(F)-S, ARM11MPCore.
'''ARM11''' is a group of [[32-bit]] [[reduced instruction set computer|RISC]] [[ARM architecture|ARM]] processor cores licensed by [[ARM Holdings]].<ref name="ARM11-Web">[https://www.arm.com/products/processors/classic/arm11/index.php ARM11 Family Webpage; ARM Holdings.]</ref> The ARM11 core family consists of ARM1136J(F)-S, ARM1156T2(F)-S, ARM1176JZ(F)-S, and ARM11MPCore. Since ARM11 cores were released from '''2002 to 2005''', they are no longer recommended for new IC designs, instead [[ARM Cortex-A]] and [[ARM Cortex-R]] cores are preferred.<ref name="ARM11-Web"/>


==Overview==
==Overview==
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| 2005 || ARM11MPCore
| 2005 || ARM11MPCore
|}
|}
{{See also|ARM architecture|List of ARM cores}}


The ARM11 [[microarchitecture]] (announced 29 April 2002) introduced the '''ARMv6''' architectural additions which had been announced in October 2001. These include [[SIMD]] media instructions, [[multiprocessor]] support and a new cache architecture. The implementation included a significantly improved instruction processing pipeline, compared to previous [[ARM9]] or [[ARM10]] families, and is used in [[smartphones]] from [[Apple Inc.|Apple]], [[Nokia]], and others. The initial ARM11 core (ARM1136) was released to licensees in October 2002.
The ARM11 product family (announced 29 April 2002) introduced the '''ARMv6''' architectural additions which had been announced in October 2001. These include [[SIMD]] media instructions, [[multiprocessor]] support, [[load-link/store-conditional|exclusive loads and stores]] instructions<ref>{{Cite web |url=https://documentation-service.arm.com/static/5e8e1e0388295d1e18d368b2 |title=ARM11 MPCore Processor Revision: r2p0 Technical Reference Manual |page=36(1-4),301-302(8-7,8-8) |accessdate=2023-12-14}}</ref> and a new cache architecture. The implementation included a significantly improved instruction processing pipeline, compared to previous [[ARM9]] or [[ARM10]] families, and is used in [[smartphones]] from [[Apple Inc.|Apple]], [[Nokia]], and others. The initial ARM11 core (ARM1136) was released to licensees in October 2002.


The ARM11 family are currently the only ARMv6-architecture cores. There are, however, ARMv6-M cores ([[ARM Cortex-M#Cortex-M0|Cortex-M0 and Cortex-M1]]), addressing [[microcontroller]] applications;<ref>not supported by Linux as of version 3.3</ref> ARM11 cores target more demanding applications.
The ARM11 family are currently the only ARMv6-architecture cores. There are, however, ARMv6-M cores ([[ARM Cortex-M#Cortex-M0|Cortex-M0 and Cortex-M1]]), addressing [[microcontroller]] applications;<ref>not supported by Linux as of version 3.3</ref> ARM11 cores target more demanding applications.


===Differences from ARM9===
===Differences from ARM9===
In terms of instruction set, ARM11 builds on the preceding [[ARM9]] generation. It incorporates all ARM926EJ-S features and adds the ARMv6 instructions for media support (SIMD) and accelerating IRQ response.
In terms of instruction set, ARM11 builds on the preceding [[ARM9]] generation. It incorporates all ARM926EJ-S features{{citation needed|date=January 2018}} and adds the ARMv6 instructions for media support (SIMD) and accelerating IRQ response.


Microarchitecture improvements in ARM11 cores<ref>"The ARM11 Microarchitecture", ARM Ltd, 2002</ref> include:
Microarchitecture improvements in ARM11 cores<ref>"The ARM11 Microarchitecture", ARM Ltd, 2002</ref> include:
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* Redesigned pipeline, supporting faster clock speeds (target up to 1&nbsp;GHz)
* Redesigned pipeline, supporting faster clock speeds (target up to 1&nbsp;GHz)
** Longer: 8 (vs 5) stages
** Longer: 8 (vs 5) stages
** Out-of-order completion for some operations (e.g. stores)
** Out-of-order completion for some operations (e.g., stores)
** Dynamic branch prediction/folding (like [[XScale]])
** Dynamic branch prediction/folding (like [[XScale]])
** Cache misses don't block execution of non-dependent instructions.
** Cache misses don't block execution of non-dependent instructions.
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[[JTAG]] debug support (for halting, stepping, breakpoints, and watchpoints) was simplified. The EmbeddedICE module was replaced with an interface which became part of the ARMv7 architecture. The hardware tracing modules (ETM and ETB) are compatible, but updated, versions of those used in the ARM9. In particular, trace semantics were updated to address parallel instruction execution and data transfers.
[[JTAG]] debug support (for halting, stepping, breakpoints, and watchpoints) was simplified. The EmbeddedICE module was replaced with an interface which became part of the ARMv7 architecture. The hardware tracing modules (ETM and ETB) are compatible, but updated, versions of those used in the ARM9. In particular, trace semantics were updated to address parallel instruction execution and data transfers.


ARM makes an effort to promote good{{by whom|date=November 2016}} [[Verilog]] coding styles and techniques. This ensures semantically rigorous designs, preserving identical semantics throughout the chip design flow, which included extensive use of [[formal verification]] techniques. Without such attention, integrating an ARM11 with third-party designs could risk exposing hard-to-find latent bugs. Due to ARM cores being integrated into many different designs, using a variety of [[logic synthesis]] tools and chip manufacturing processes, the impact of its [[register-transfer level]] (RTL) quality is magnified many times.<ref name="X">''The Dangers of Living with an X (bugs hidden in your Verilog)'', Version 1.1 (14 October 2003).</ref> The ARM11 generation focused more on synthesis than previous generations, making such concerns be more of an issue.
ARM makes an effort to promote recommended [[Verilog]] coding styles and techniques. This ensures semantically rigorous designs, preserving identical semantics throughout the chip design flow, which included extensive use of [[formal verification]] techniques. Without such attention, integrating an ARM11 with third-party designs could risk exposing hard-to-find latent bugs. Due to ARM cores being integrated into many different designs, using a variety of [[logic synthesis]] tools and chip manufacturing processes, the impact of its [[register-transfer level]] (RTL) quality is magnified many times.<ref name="X">''The Dangers of Living with an X (bugs hidden in your Verilog)'', Version 1.1 (14 October 2003).</ref> The ARM11 generation focused more on synthesis than previous generations, making such concerns more of an issue.


==Cores==
==Cores==
There are four ARM11 cores:
There are four ARM11 cores:
* ARM1136<ref name="arm1136">[http://infocenter.arm.com/help/topic/com.arm.doc.ddi0211k/DDI0211K_arm1136_r1p5_trm.pdf ARM1136JF-S and ARM1136J-S Technical Reference Manual] Revision: r1p5; ARM DDI 0211K</ref>
* ARM1136<ref name="arm1136">{{cite web|url=https://developer.arm.com/documentation/ddi0211/k/|title=ARM1136JF-S and ARM1136J-S Technical Reference Manual Revision: r1p5; ARM DDI 0211K}}</ref>
* ARM1156, introduced Thumb2 instructions
* ARM1156, introduced Thumb2 instructions
* ARM1176, introduced security extensions<ref>[http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301h/DDI0301H_arm1176jzfs_r0p7_trm.pdf ARM1176JZF-6 Technical Reference Manual] Revision: r0p7; accessed on 4 October 2012.</ref>
* ARM1176, introduced security extensions<ref>{{cite web|url=https://developer.arm.com/documentation/ddi0301/h/|title=ARM1176JZF-S Technical Reference Manual Revision: r0p7|access-date=4 October 2012}}</ref>
* ARM11MPcore, introduced multicore support
* ARM11MPcore, introduced multicore support


==Chips==
==Chips==
[[File:Raspberry Pi B+ top.jpg|thumb|right|Raspberry Pi B+ with a Broadcom BCM2835 (ARM1176JZF-S) {{fact|date=November 2015}}]]
[[File:Raspberry Pi B+ top.jpg|thumb|Raspberry Pi B+ with a Broadcom BCM2835 (ARM1176JZF-S)<ref>{{Cite web|url=https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2835/README.md|title=BCM2835 – Raspberry Pi Documentation|website=raspberrypi.org|language=en-GB|access-date=2017-04-15}}</ref>]]
[[File:KraftCom CoaxLine Adapter CN-KE502M - Atheros AR7400-AG2C-9835.jpg|thumb|Atheros AR7400]]
[[File:Garmin Edge Explore - board - STMicroelectronics STA2065N2-1727.jpg|thumb|[[STMicroelectronics]] STA2065N2 (ARM1176) with embedded [[GPS]]]]
{{expand list|date=December 2011}}
{{expand list|date=December 2011}}
{{unreferenced|section|date=November 2015}}
{{unreferenced section|date=November 2015}}
* [[Ambarella Inc.|Ambarella]] A5s, A7, A7L
* [[Ambarella Inc.|Ambarella]] A5s, A7, A7L
* ASPEED Technology Inc. AST25xx
* ASPEED Technology Inc. AST25xx
* [[Broadcom]] BCM2835 ([[Raspberry Pi]]), BCM21553
* [[Broadcom]] BCM2835 ([[Raspberry Pi]] 1 A/B, Pi Zero), BCM21553
* [[Cavium]] ECONA CNS3000 series <ref>{{cite press release|url=http://www.cavium.com/newsevents_Caviumnetworks_ECONA-CNS3XXX.html|title=Cavium Networks Introduces ECONA Family of Super Energy Efficient ARM®-Based System-on-Chip (SoC) Processors for the Digital Home that break the 1 Watt Barrier|date=September 8, 2009|publisher=[[Cavium]]}}</ref>
* [[Cavium]] ECONA CNS3000 series<ref>{{cite press release|url=http://www.cavium.com/newsevents_Caviumnetworks_ECONA-CNS3XXX.html|title=Cavium Networks Introduces ECONA Family of Super Energy Efficient ARM-Based System-on-Chip (SoC) Processors for the Digital Home that break the 1 Watt Barrier|date=8 September 2009|publisher=[[Cavium]]|access-date=14 November 2015|archive-date=17 November 2015|archive-url=https://web.archive.org/web/20151117031603/http://www.cavium.com/newsevents_Caviumnetworks_ECONA-CNS3XXX.html|url-status=dead}}</ref>
* [[CSR plc|CSR]] Quatro 4230, 45xx, 53xx
* [[CSR plc|CSR]] Quatro 4230, 45xx, 53xx
* [[Freescale Semiconductor]] i.MX3x series, such as [[i.MX31]], [[I.MX#i.MX35_family|i.MX35]]
* [[Freescale Semiconductor]] i.MX3x series, such as [[i.MX31]], [[I.MX#i.MX35 family|i.MX35]]
⚫
* [[Nintendo]] CTR-CPU ([[Nintendo 3DS]] CPU)
* Infotmic IMAPX2xx
* Infotmic IMAPX2xx
⚫
* [[Nintendo]] CTR-CPU ([[Nintendo 3DS]], [[New Nintendo 3DS]])
* [[NTC Module]] [[NeuroMatrix|1879VYa1Ya, K1879KhB1Ya, 1879KhK1Ya, K1888VS018]]
* [[Nvidia]] [[Tegra]]
* [[Nvidia]] [[Tegra]]
⚫
* [[MediaTek]] MT6276, MT6573
* Mindspeed Comcerto 1000 (Freescale LS102MA)
* Philips Semiconductor/[[NXP]]/[[ST-NXP Wireless]] [[Nomadik]] STn8820
* [[PLX Technology]] NAS782x
* [[PLX Technology]] NAS782x
⚫
* [[MediaTek]] MTK6573
* [[Qualcomm]] MSM720x, MSM7x27
* [[Qualcomm]] MSM720x, MSM7x27
* [[Qualcomm Atheros]] AR7400
* [[Qualcomm Atheros]] AR7400
* [[Samsung]] S3C64xx, S5P64xx, S5L87xx, S5L89xx or Exynos Dual with Logic11
* [[Samsung]] S3C64xx, S5P64xx, S5L87xx, S5L89xx or Exynos Dual with Logic11
* [[Telechips]] TCC8902
* [[Telechips]] TCC8902
⚫
* [[Xcometic]] KVM2800
* [[Texas Instruments]] [[OMAP|OMAP2]] series, with a [[Texas Instruments TMS320|TMS320]] C55x or C64x [[digital signal processor|DSP]] as a second core
* [[Texas Instruments]] [[OMAP|OMAP2]] series, with a [[Texas Instruments TMS320|TMS320]] C55x or C64x [[digital signal processor|DSP]] as a second core
* [[iPhone 3G]] series, with a Samsung ARM 1176JZ chip
⚫
* Xcometic KVM2800


==See also==
==See also==
{{Portal|Computer science|Electronics}}
{{Portal|Electronics}}
* [[ARM architecture]]
* [[ARM architecture]]
⚫
* [[List of ARM microarchitectures|List of ARM architectures and cores]]
* [[Joint Test Action Group|JTAG]]
* [[Interrupt]], [[Interrupt handler]]
* [[Interrupt]], [[Interrupt handler]]
* [[JTAG]]
⚫
* [[List of ARM microarchitectures|List of ARM architectures and cores]]
* [[Real-time operating system]], [[Comparison of real-time operating systems]]
* [[Real-time operating system]], [[Comparison of real-time operating systems]]


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;ARM11 official documents
;ARM11 official documents
* {{Official website|http://www.arm.com/products/processors/classic/arm11/index.php|ARM11 official website}}
* {{Official website|http://www.arm.com/products/processors/classic/arm11/index.php|ARM11 official website}}
* Architecture Reference Manuals: [https://silver.arm.com/download/ARM_Architecture/AR550-DA-70002-r0p0-00rel0/DDI%2001001.pdf ARMv4/5/6], [https://silver.arm.com/download/ARM_and_AMBA_Architecture/AR570-DA-70000-r0p0-00rel2/DDI0406C_C_arm_architecture_reference_manual.pdf ARMv7-A/R]
* [http://infocenter.arm.com/help/topic/com.arm.doc.set.arm11/index.html ARM11 Technical Reference Manuals]
* Core Reference Manuals: [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0211k/DDI0211K_arm1136_r1p5_trm.pdf ARM1136J(F)-S], [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0338g/DDI0338G_arm1156t2s_r0p4_trm.pdf ARM1156T2-S], [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0290g/DDI0290G_arm1156t2fs_r0p4_trm.pdf ARM1156T2F-S], [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0333h/DDI0333H_arm1176jzs_r0p7_trm.pdf ARM1176JZ-S], [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301h/DDI0301H_arm1176jzfs_r0p7_trm.pdf ARM1176JZF-S], [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0360f/DDI0360F_arm11_mpcore_r2p0_trm.pdf ARM11 MPCore]
* [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html ARMv6 Architecture Reference Manual] (requires registration)
* Coprocessor Reference Manual: [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0274h/DDI0274H_vfp11_r1p5_trm.pdf VFP11 (Floating-Point for ARM1136JF-S)]


;Quick Reference Cards
;Quick Reference Cards
Line 102: Line 112:


;Other
;Other
* [http://wanderingcoder.net/2010/07/19/ought-arm/ ARM11 lacks an integer hardware division instruction]
* [http://wanderingcoder.net/2010/07/19/ought-arm/ ARM11 lacks an integer hardware division instruction] {{Webarchive|url=https://web.archive.org/web/20200704000617/http://wanderingcoder.net/2010/07/19/ought-arm/ |date=4 July 2020 }}
* Yurichev, Dennis, "An Introduction To Reverse Engineering for Beginners" including ARM assembly. Online book: http://yurichev.com/writings/RE_for_beginners-en.pdf
* [http://www.cs.virginia.edu/~skadron/cs433_s09_processors/arm11.pdf The ARM11 Architecture], 2009, by Ian Davey and Payton Oliveri
* [http://www.cs.virginia.edu/~skadron/cs433_s09_processors/arm11.pdf The ARM11 Architecture], 2009, by Ian Davey and Payton Oliveri


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{{Clear}}
{{Clear}}


⚫
{{use dmy dates|date=February 2012}}
{{DEFAULTSORT:Arm11}}
{{DEFAULTSORT:Arm11}}

[[Category:ARM cores]]
[[Category:2002 introductions]]
[[Category:ARM processors]]
[[Category:32-bit microprocessors]]

Revision as of 06:49, 2 August 2024

ARM11
General information
Designed byARM Holdings
Architecture and classification
MicroarchitectureARMv6, ARMv6T2, ARMv6Z, ARMv6K
Instruction setARM (32-bit),
Thumb (16-bit),
Thumb-2 (32-bit)

ARM11 is a group of 32-bit RISC ARM processor cores licensed by ARM Holdings.[1] The ARM11 core family consists of ARM1136J(F)-S, ARM1156T2(F)-S, ARM1176JZ(F)-S, and ARM11MPCore. Since ARM11 cores were released from 2002 to 2005, they are no longer recommended for new IC designs, instead ARM Cortex-A and ARM Cortex-R cores are preferred.[1]

Overview

Announced
Year Core
2002 ARM1136J(F)-S
2003 ARM1156T2(F)-S
2003 ARM1176JZ(F)-S
2005 ARM11MPCore
See also: ARM architecture and List of ARM cores

The ARM11 product family (announced 29 April 2002) introduced the ARMv6 architectural additions which had been announced in October 2001. These include SIMD media instructions, multiprocessor support, exclusive loads and stores instructions[2] and a new cache architecture. The implementation included a significantly improved instruction processing pipeline, compared to previous ARM9 or ARM10 families, and is used in smartphones from Apple, Nokia, and others. The initial ARM11 core (ARM1136) was released to licensees in October 2002.

The ARM11 family are currently the only ARMv6-architecture cores. There are, however, ARMv6-M cores (Cortex-M0 and Cortex-M1), addressing microcontroller applications;[3] ARM11 cores target more demanding applications.

Differences from ARM9

In terms of instruction set, ARM11 builds on the preceding ARM9 generation. It incorporates all ARM926EJ-S features[citation needed] and adds the ARMv6 instructions for media support (SIMD) and accelerating IRQ response.

Microarchitecture improvements in ARM11 cores[4] include:

  • SIMD instructions which can double MPEG-4 and audio digital signal processing algorithm speed
  • Cache is physically addressed, solving many cache aliasing problems and reducing context switch overhead.
  • Unaligned and mixed-endian data access is supported.
  • Reduced heat production and lower overheating risk
  • Redesigned pipeline, supporting faster clock speeds (target up to 1 GHz)
    • Longer: 8 (vs 5) stages
    • Out-of-order completion for some operations (e.g., stores)
    • Dynamic branch prediction/folding (like XScale)
    • Cache misses don't block execution of non-dependent instructions.
    • Load/store parallelism
    • ALU parallelism
  • 64-bit data paths

JTAG debug support (for halting, stepping, breakpoints, and watchpoints) was simplified. The EmbeddedICE module was replaced with an interface which became part of the ARMv7 architecture. The hardware tracing modules (ETM and ETB) are compatible, but updated, versions of those used in the ARM9. In particular, trace semantics were updated to address parallel instruction execution and data transfers.

ARM makes an effort to promote recommended Verilog coding styles and techniques. This ensures semantically rigorous designs, preserving identical semantics throughout the chip design flow, which included extensive use of formal verification techniques. Without such attention, integrating an ARM11 with third-party designs could risk exposing hard-to-find latent bugs. Due to ARM cores being integrated into many different designs, using a variety of logic synthesis tools and chip manufacturing processes, the impact of its register-transfer level (RTL) quality is magnified many times.[5] The ARM11 generation focused more on synthesis than previous generations, making such concerns more of an issue.

Cores

There are four ARM11 cores:

  • ARM1136[6]
  • ARM1156, introduced Thumb2 instructions
  • ARM1176, introduced security extensions[7]
  • ARM11MPcore, introduced multicore support

Chips

Raspberry Pi B+ with a Broadcom BCM2835 (ARM1176JZF-S)[8]
Atheros AR7400
STMicroelectronics STA2065N2 (ARM1176) with embedded GPS

See also

References

  1. ^ a b ARM11 Family Webpage; ARM Holdings.
  2. ^ "ARM11 MPCore Processor Revision: r2p0 Technical Reference Manual". p. 36(1-4),301-302(8-7,8-8). Retrieved 14 December 2023.
  3. ^ not supported by Linux as of version 3.3
  4. ^ "The ARM11 Microarchitecture", ARM Ltd, 2002
  5. ^ The Dangers of Living with an X (bugs hidden in your Verilog), Version 1.1 (14 October 2003).
  6. ^ "ARM1136JF-S and ARM1136J-S Technical Reference Manual Revision: r1p5; ARM DDI 0211K".
  7. ^ "ARM1176JZF-S Technical Reference Manual Revision: r0p7". Retrieved 4 October 2012.
  8. ^ "BCM2835 – Raspberry Pi Documentation". raspberrypi.org. Retrieved 15 April 2017.
  9. ^ "Cavium Networks Introduces ECONA Family of Super Energy Efficient ARM-Based System-on-Chip (SoC) Processors for the Digital Home that break the 1 Watt Barrier" (Press release). Cavium. 8 September 2009. Archived from the original on 17 November 2015. Retrieved 14 November 2015.
Wikimedia Commons has media related to ARM11.
ARM11 official documents
Quick Reference Cards
  • Instructions: Thumb (1), ARM and Thumb-2 (2), Vector Floating Point (3)
  • Opcodes: Thumb (1, 2), ARM (3, 4), GNU Assembler Directives 5.
Other
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