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Both the older and newer chips can use 6 threads per tile{{what?}} (for a total of 7,296 and 8,832 threads, respectively) "[[Multiple instruction, multiple data|MIMD]] (Multiple Instruction, Multiple Data) parallelism and has distributed, local memory as its only form of memory on the device" (except for registers).{{cn}} The older GC2 chip has 256 KiB per tile while the newer GC200 chip has about 630 KiB per tile that are arranged into ''islands'' (4 tiles per island),<ref>{{Cite arXiv|title=Dissecting theGraphcore IPUArchitecturevia Microbenchmarking|eprint=1912.03413|last1=Jia|first1=Zhe|last2=Tillman|first2=Blake|last3=Maggioni|first3=Marco|author4=Daniele Paolo Scarpazza|year=2019|class=cs.DC }}</ref> that are arranged into columns, and latency is best within tile.{{what?}}{{cn}} The IPU uses IEEE [[Half-precision floating-point format|FP16]], with stochastic rounding, and also [[Single-precision floating-point format|single-precision FP32]], at lower performance.<ref>{{Cite web|title=THE GRAPHCORE SECOND GENERATION IPU|url=https://www.graphcore.ai/hubfs/MK2-%20The%20Graphcore%202nd%20Generation%20IPU%20Final%20v7.14.2020.pdf?hsLang=en}}</ref> Code and data executed locally must fit in a tile, but with message-passing, all on-chip or off-chip memory can be used, and software for AI makes it transparently possible,{{what?}} e.g. has [[PyTorch]] support.{{cn}}
Both the older and newer chips can use 6 threads per tile{{what?|date=July 2024}} (for a total of 7,296 and 8,832 threads, respectively) "[[Multiple instruction, multiple data|MIMD]] (Multiple Instruction, Multiple Data) parallelism and has distributed, local memory as its only form of memory on the device" (except for registers).{{cn|date=July 2024}} The older GC2 chip has 256 KiB per tile while the newer GC200 chip has about 630 KiB per tile that are arranged into ''islands'' (4 tiles per island),<ref>{{Cite arXiv|title=Dissecting theGraphcore IPUArchitecturevia Microbenchmarking|eprint=1912.03413|last1=Jia|first1=Zhe|last2=Tillman|first2=Blake|last3=Maggioni|first3=Marco|author4=Daniele Paolo Scarpazza|year=2019|class=cs.DC }}</ref> that are arranged into columns, and latency is best within tile.{{what?|date=July 2024}}{{cn|date=July 2024}} The IPU uses IEEE [[Half-precision floating-point format|FP16]], with stochastic rounding, and also [[Single-precision floating-point format|single-precision FP32]], at lower performance.<ref>{{Cite web|title=THE GRAPHCORE SECOND GENERATION IPU|url=https://www.graphcore.ai/hubfs/MK2-%20The%20Graphcore%202nd%20Generation%20IPU%20Final%20v7.14.2020.pdf?hsLang=en}}</ref> Code and data executed locally must fit in a tile, but with message-passing, all on-chip or off-chip memory can be used, and software for AI makes it transparently possible,{{what?|date=July 2024}} e.g. has [[PyTorch]] support.{{cn|date=July 2024}}


==See also==
==See also==

Latest revision as of 11:29, 12 July 2024

Graphcore Limited
Company typePrivate
IndustrySemiconductors
Founded2016; 8 years ago (2016)
Founders
  • Nigel Toon
  • Simon Knowles
Headquarters
Bristol
,
United Kingdom
Key people
  • Nigel Toon (CEO)
  • Simon Knowles (CTO)
ProductsIPU, Poplar
RevenueUS$2.7 million (2022)[1]
US$−205 million (2022)[1]
Number of employees
494 (2023)[1]
Websitewww.graphcore.ai

Graphcore Limited is a British semiconductor company that develops accelerators for AI and machine learning. It has introduced a massively parallel Intelligence Processing Unit (IPU) that holds the complete machine learning model inside the processor.[2]

History

[edit]

Graphcore was founded in 2016 by Simon Knowles and Nigel Toon.[3]

In the autumn of 2016, Graphcore secured a first funding round led by Robert Bosch Venture Capital. Other backers included Samsung, Amadeus Capital Partners, C4 Ventures, Draper Esprit, Foundation Capital, and Pitango.[4][5]

In July 2017, Graphcore secured a round B funding led by Atomico,[6] which was followed a few months later by $50 million in funding from Sequoia Capital.[7]

In December 2018, Graphcore closed its series D with $200 million raised at a $1.7 billion valuation, making the company a unicorn. Investors included Microsoft, Samsung and Dell Technologies.[8]

On 13 November 2019, Graphcore announced that their Graphcore C2 IPUs were available for preview on Microsoft Azure.[9]

Meta Platforms acquired the AI networking technology team from Graphcore in early 2023.[10]

In July 2024, Softbank Group agreed to acquire Graphcore for around $500 million. The deal is under review by the UK's Business Department's investment security unit.[11][12]

Products

[edit]

In 2016, Graphcore announced the world's first graph tool chain designed for machine intelligence called Poplar Software Stack.[13][14][15]

In July 2017, Graphcore announced its first chip, called the Colossus GC2, a "16 nm massively parallel, mixed-precision floating point processor", that became available in 2018.[16][17] Packaged with two chips on a single PCI Express card, called the Graphcore C2 IPU (an Intelligence Processing Unit), it is stated to perform the same role as a GPU in conjunction with standard machine learning frameworks such as TensorFlow.[16] The device relies on scratchpad memory for its performance rather than traditional cache hierarchies.[18]

In July 2020, Graphcore presented its second generation processor called GC200, built with TSMC's 7nm FinFET manufacturing process. GC200 is a 59 billion transistor, 823 square-millimeter integrated circuit with 1,472 computational cores and 900 Mbyte of local memory.[19] In 2022, Graphcore and TSMC presented the Bow IPU, a 3D package of a GC200 die bonded face to face to a power-delivery die that allows for higher clock rate at lower core voltage.[20] Graphcore aims at a Good machine, named after I.J. Good, enabling AI models with more parameters than the human brain has synapses.[20]

Release date Product Process node Cores Threads Transistors teraFLOPS (FP16)
July 2017 Colossus™ MK1 - GC2 IPU 16 nm TSMC 1216 7296 ? ~100-125[21]
July 2020 Colossus™ MK2 - GC200 IPU 7 nm TSMC 1472 8832 59 billion ~250-280[22]
Colossus™ MK3 ~500[23]

Both the older and newer chips can use 6 threads per tile[clarification needed] (for a total of 7,296 and 8,832 threads, respectively) "MIMD (Multiple Instruction, Multiple Data) parallelism and has distributed, local memory as its only form of memory on the device" (except for registers).[citation needed] The older GC2 chip has 256 KiB per tile while the newer GC200 chip has about 630 KiB per tile that are arranged into islands (4 tiles per island),[24] that are arranged into columns, and latency is best within tile.[clarification needed][citation needed] The IPU uses IEEE FP16, with stochastic rounding, and also single-precision FP32, at lower performance.[25] Code and data executed locally must fit in a tile, but with message-passing, all on-chip or off-chip memory can be used, and software for AI makes it transparently possible,[clarification needed] e.g. has PyTorch support.[citation needed]

See also

[edit]

References

[edit]
  1. ^ a b c Cherney, Max A. (5 October 2023). "Losses widen, cash needed at chip startup Graphcore, an Nvidia rival, filing shows". Reuters.
  2. ^ Peter Clarke (2016-11-01). "AI Chip Startup Shares Insights: "Very large" FinFET chip in the works at TSMC". eetimes. Retrieved 2017-08-02.
  3. ^ Jolly, Jasper (2020-12-29). "UK chipmaker Graphcore valued at $2.8bn after it raises $222m". The Guardian.
  4. ^ Arjun Kharpal (2016-10-31). "AI chipmaker Graphcore raises $30 million to take on Intel". CNBC. Retrieved 2017-07-31.
  5. ^ Madhumita Murgia (2016-10-31). "UK chip start-up Graphcore raises £30m for take on AI giants". Financial Times. Retrieved 2017-08-02.
  6. ^ Jeremy Kahn and Ian King (2017-07-20). "U.K. Chip Designer Graphcore Gets $30 Million to Fund Expansion". Bloomberg. Retrieved 2017-07-31.
  7. ^ Lynley, Matthew (2017-11-12). "Graphcore raises $50M amid a flurry of AI chip activity". TechCrunch. Retrieved 2017-12-07.
  8. ^ "AI chip startup Graphcore closes $200M Series D, adds BMW and Microsoft as strategic investors". TechCrunch. 18 December 2018. Retrieved 2018-12-19.
  9. ^ Toon, Nigel. "Microsoft and Graphcore collaborate to accelerate Artificial Intelligence". www.graphcore.ai. Retrieved 2019-11-16.
  10. ^ Paul, Katie (5 May 2023). "Meta Platforms scoops up AI networking chip team from Graphcore". Reuters.
  11. ^ Nicol-Schwarz, Kai (9 July 2024). "Graphcore employees have share value wiped as sale to SoftBank agreed". Sifted.
  12. ^ Titcomb, James; Field, Matthew (1 July 2024). "Japanese deal for AI champion Graphcore faces national security review". The Daily Telegraph.
  13. ^ Fyles, Matt. "Inside an AI 'brain' - What does machine learning look like?". www.graphcore.ai. Retrieved 2019-11-16.
  14. ^ Doherty, Sally. "Introducing Poplar® - our IPU-Processor software at NeurIPS". www.graphcore.ai. Retrieved 2019-11-16.
  15. ^ Fyles, Matt. "Graph computing for machine intelligence with Poplar™". www.graphcore.ai. Retrieved 2019-11-16.
  16. ^ a b Trader, Tiffany (2017-07-20). "Graphcore Readies Launch of 16nm Colossus-IPU Chip". hpcwire.com. HPC Wire. Retrieved 2017-12-11.
  17. ^ Lucchesi, Ray (2018-11-19). "New GraphCore GC2 chips with 2PFlop performance in a Dell Server". silvertonconsulting.com. Silverton Consulting. Retrieved 2018-12-16.
  18. ^ Citadel High Performance Computing R&D Team (2019). "Dissecting the Graphcore IPU Architecture via Microbenchmarking" (PDF).
  19. ^ "Graphcore Introducing 2nd Generation IPU Systems For AI At Scale". Retrieved 2020-08-09.
  20. ^ a b Timothy Prickett Morgan: GraphCore Goes Full 3D With AI Chips. The Next Platform, March 3, 2022.
  21. ^ Kennedy, Patrick (2019-06-07). "Hands-on With a Graphcore C2 IPU PCIe Card at Dell Tech World". ServeTheHome. Retrieved 2023-06-26.
  22. ^ Ltd, Graphcore. "IPU Processors". www.graphcore.ai. Retrieved 2023-06-26.
  23. ^ "ScalAH22: 13th Workshop on Latest Advances in Scalable Algorithms for Large-Scale Heterogeneous Systems". www.csm.ornl.gov. Retrieved 2023-06-26.
  24. ^ Jia, Zhe; Tillman, Blake; Maggioni, Marco; Daniele Paolo Scarpazza (2019). "Dissecting theGraphcore IPUArchitecturevia Microbenchmarking". arXiv:1912.03413 [cs.DC].
  25. ^ "THE GRAPHCORE SECOND GENERATION IPU" (PDF).
[edit]

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