Intel Quartus Prime: Difference between revisions

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Intel Quartus Prime is programmable logic device design software produced by Intel; prior to Intel's acquisition of Altera the tool was called Altera Quartus Prime, earlier Altera Quartus II. Quartus Prime enables analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. Quartus Prime includes an implementation of VHDL and Verilog for hardware description, visual editing of logic circuits, and vector waveform simulation.

Features

Quartus Prime software features include:

Platform Designer (previously QSys, previously SOPC Builder), a tool that eliminates manual system integration tasks by automatically generating interconnect logic and creating a testbench to verify functionality.
SoCEDS, a set of development tools, utility programs, run-time software, and application examples to help you develop software for SoC FPGA embedded systems.
DSP Builder, a tool that creates a seamless bridge between the MATLAB/Simulink tool and Quartus Prime software, so FPGA designers have the algorithm development, simulation, and verification capabilities of MATLAB/Simulink system-level design tools
External memory interface toolkit, which identifies calibration issues and measures the margins for each DQS signal.
Generation of JAM/STAPL files for JTAG in-circuit device programmers.

Editions

Lite Edition

The Lite Edition is the free version of Quartus Prime. This edition provides compilation and programming for a limited number of Intel FPGA devices. The low-cost Cyclone family of FPGAs is fully supported by this edition, as well as the MAX family of CPLDs, meaning small developers and educational institutions have no overheads from the cost of development software.

Standard Edition

The Standard Edition supports an extensive number of FPGA devices but requires a license.

Pro Edition

The Pro Edition supports only the latest FPGA devices.

External links

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+{{short description|Programmable logic device design software by Intel}}
-'''Altera Quartus II''' is [[programmable logic device]] design software produced by [[Altera]]. Quartus II enables analysis and synthesis of [[Hardware description language|HDL]] designs, which enables the developer to compile their designs, perform timing analysis, examine [[Register-transfer level|RTL]] diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. Quartus includes an implementation of [[VHDL]] and [[Verilog]] for hardware description, visual editing of logic circuits, and vector waveform simulation.
+'''Intel Quartus Prime''' is [[programmable logic device]] design software produced by [[Intel]]; prior to Intel's acquisition of Altera the tool was called '''Altera Quartus Prime''', earlier '''Altera Quartus&nbsp;II'''. Quartus Prime enables analysis and synthesis of [[Hardware description language|HDL]] designs, which enables the developer to compile their designs, perform timing analysis, examine [[Register-transfer level|RTL]] diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. Quartus Prime includes an implementation of [[VHDL]] and [[Verilog]] for hardware description, visual editing of logic circuits, and vector waveform simulation.
 ==Features==
-Quartus&nbsp;II software features include:
+Quartus Prime software features include:
-* '''SOPC Builder''', a tool in Quartus II software that eliminates manual system integration tasks by automatically generating interconnect logic and creating a testbench to verify functionality
+* Platform Designer (previously QSys, previously SOPC Builder), a tool that eliminates manual system integration tasks by automatically generating interconnect logic and creating a testbench to verify functionality.
-* Qsys, a system-integration tool that is the next generation of SOPC Builder. It uses an FPGA-optimized network-on-chip architecture that doubles the fMAX performance vs. SOPC Builder.
 * SoCEDS, a set of development tools, utility programs, run-time software, and application examples to help you develop software for [[System on a chip|SoC]] FPGA embedded systems.
-* [[Digital signal processing|DSP]] Builder, a tool that creates a seamless bridge between the [[MATLAB]]/Simulink tool and Quartus&nbsp;II software, so FPGA designers have the algorithm development, simulation, and verification capabilities of MATLAB/Simulink system-level design tools
+* [[Digital signal processing|DSP]] Builder, a tool that creates a seamless bridge between the [[MATLAB]]/Simulink tool and Quartus Prime software, so FPGA designers have the algorithm development, simulation, and verification capabilities of MATLAB/Simulink system-level design tools
 * External memory interface toolkit, which identifies calibration issues and measures the margins for each DQS signal.
-* Generation of [[Standard Test and Programming Language|JAM/STAPL]] files for [[Joint Test Action Group|JTAG]] in-circuit device programmers.
+* Generation of [[Standard Test and Programming Language|JAM/STAPL]] files for [[JTAG]] in-circuit device programmers.
-===SOPC Builder===
-'''SOPC Builder''' (System on a Programmable Chip Builder) is software made by [[Altera]] that automates connecting soft-hardware components to create a complete computer system that runs on any of its various [[Field-programmable gate array|FPGA]] chips. SOPC Builder incorporates a library of pre-made components (including the flagship [[Nios II]] [[soft processor]], [[memory controller]]s, interfaces, and peripherals) and an interface for incorporating custom ones. Interconnections are made though the [[Avalon bus]]. Bus arbitration, bus width matching, and even [[clock domain crossing]] are all handled automatically when SOPC Builder generates the system. A [[GUI]] is the only thing used to configure the soft-hardware components (which often have many options) and to specify the [[bus topology]].
-The resulting "virtual" system can then be connected to the outside world via the FPGA's programmable pins or connected internally to other soft components. The FPGA's pins are routed to connectors, such as for PCI or DDR, or—as is often the case in embedded systems—to other chips mounted on the same PCB.
-Resource utilization on an FPGA hosting an SOPC Builder system is very modest by modern standards. FPGA devices supporting SOPC systems include almost all Altera FPGAs (and even some CPLDs) ranging from $5 to $5,000 in price.
 ==Editions==
-===Web Edition===
+===Lite Edition===
+The Lite Edition is the free version of Quartus Prime. This edition provides compilation and programming for a limited number of Intel FPGA devices. The low-cost Cyclone family of [[Field-programmable gate array|FPGA]]s is fully supported by this edition, as well as the MAX family of [[Complex programmable logic device|CPLD]]s, meaning small developers and educational institutions have no overheads from the cost of development software.
-The Web Edition is a free version of Quartus II that can be downloaded or delivered by mail for free.
-This edition provided compilation and programming for a limited number of [[Altera]] devices.
-The low-cost Cyclone family of [[Field-programmable gate array|FPGA]]s is fully supported by this edition, as well as the MAX family of [[Complex programmable logic device|CPLD]]s, meaning small developers and educational institutions have no overheads from the cost of development software.
-License registration is required to use the Web Edition of Quartus II, which is free and can be renewed an unlimited number of times.
-===Subscription Edition===
+===Standard Edition===
+The Standard Edition supports an extensive number of FPGA devices but requires a license.
-The Subscription Edition is also available for free download, but a DRMed license must be paid for to use the full functionality in the software.  The free Web Edition license can be used on this software, restricting the devices that can be used.
+===Pro Edition===
-The supported operating systems are:
+The Pro Edition supports only the latest FPGA devices.
-* Microsoft Windows Vista (32-bit and 64-bit)
-* Microsoft Windows XP (32-bit and 64-bit)
-* Microsoft Windows 2000
-* Solaris 8 and 9 (32-bit and 64-bit)
-* SUSE Linux Enterprise 9 (32-bit and 64-bit)
-* Red Hat Enterprise Linux 5 (32-bit and 64-bit)
-* Red Hat Enterprise Linux 4 (32-bit and 64-bit)
-* Red Hat Enterprise Linux 3 (32-bit and 64-bit)
 ==See also==
 * [[Xilinx ISE]]
+* [[Xilinx Vivado]]
+* [[ModelSim]]
 ==External links==
-*[https://web.archive.org/web/20080820054140/http://www.altera.com/products/software/products/quartus2 Altera Quartus II website]
+*[https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html Intel Quartus Prime Software]
-*[http://www.altera.com/ Altera official website]
+*[https://www.intel.com/content/www/us/en/products/programmable.html Intel FPGAs and Programmable Devices official website]
-*[https://help.ubuntu.com/community/QuartusII Installation Tutorial on Ubuntu 8.04]
 {{Programmable Logic}}
 [[Category:Electronic design automation software]]
+[[Category:Proprietary software that uses Qt]]
 [[Category:Software that uses Qt]]