CAS latency: Difference between revisions

'''Column Address Strobe (CAS) latency''', or '''CL''', is the delay time between the READ command and the moment data is available.<ref>{{cite web|url=http://archive.arstechnica.com/paedia/r/ram_guide/ram_guide.part2-5.html|title=Ars Technica RAM Guide Part II: Asynchronous and Synchronous DRAM|last=Stokes|first=Jon "Hannibal"|publisher=Ars Technica|date=1998-20041998–2004}}</ref><ref name=umd>{{citation|title=Synchronous DRAM Architectures, Organizations, and Alternative Technologies|publisher=University of Maryland|last=Jacob|first=Bruce L.|date=December 10, 2002|url=https://user.eng.umd.edu/~blj/CS-590.26/references/DRAM-Systems.pdf}}</ref> In asynchronous [[Dynamic random access memory|DRAM]], the interval is specified in nanoseconds (absolute time).<ref name=async>{{citation |title=Memory technology evolution: an overview of system memory technologies|publisher=HP|date=July 2008|url=https://support.hpe.com/hpsc/doc/public/display?docId=emr_na-c01552458}}</ref> In [[SDRAM|synchronous DRAM]], the interval is specified in clock cycles. Because the latency is dependent upon a number of clock ticks instead of absolute time, the actual time for an [[SDRAM]] module to respond to a CAS event might vary between uses of the same module if the clock rate differs.

Because memory modules have multiple internal banks, and data can be output from one during access latency for another, the output pins can be kept 100% busy regardless of the CAS latency through [[Pipeline (computing)|pipelining]]; the maximum attainable [[Bandwidth (computing)|bandwidth]] is determined solely by the clock speed. Unfortunately, this maximum bandwidth can only be attained if the address of the data to be read is known long enough in advance; if the address of the data being accessed is not predictable, [[pipeline stall]]s can occur, resulting in a loss of bandwidth. For a completely unknown memory access (AKA Random access), the relevant latency is the time to close any open row, plus the time to open the desired row, followed by the CAS latency to read data from it. Due to [[Locality_of_referenceLocality of reference|spatial locality]], however, it is common to access several words in the same row. In this case, the CAS latency alone determines the elapsed time.

|align=right| 100 &nbsp;MHz

|align=right| 133 &nbsp;MHz