CAS latency: Difference between revisions

 

==Effect on memory access speed==

With asynchronous DRAM, memory was accessed by a memory controller on the memory bus based on a set timing rather than a clock, and was separate from the system bus.<ref name=async/> [[SDRAM|Synchronous DRAM]], however, has a CAS latency that is dependent upon the clock rate. Accordingly, the CAS latency of an [[SDRAM]] memory module is specified in clock ticks instead of absolute time. {{citation needed|date=August 2019}}