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==Description==
As initially introduced, the Level 6 consisted of three models: the 6/06, the 6/34, and the 6/36. The CPU featured a [[real-time clock]], a [[Read-only memory|ROM]] [[bootstrap loader]] and 64 [[Interrupt priority level|interrupt levels]]. The architecture provided a variety of [[addressing mode]]s and 18 programmer-visible [[Processor register|registers]]. [[Rack-mount]] and tabletop versions were available.
These systems supported up to 64 K [[word (computer architecture)|word]]s (KW) of [[Metal–oxide–semiconductor#Metal–oxide–semiconductor structure|MOS]] memory with a cycle time of 650 nanoseconds.
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