Revision as of 10:38, 27 March 2022 edit BeforeAdapter (talk \| contribs) Extended confirmed users 1,075 edits Tables are hard ← Previous edit		Revision as of 00:03, 23 July 2022 edit undo 83.21.5.253 (talk) →Memory timing examples Next edit →
Line 225: {{CAS latency/row\|3300\|0\|16}} \|- ! scope="row" rowspan="5052" \| [[DDR4 SDRAM]] \|- {{CAS latency/group\|3\|DDR4\|1600\|0}} Line 324: {{CAS latency/row\|3866\|2\|18}} \|- {{CAS latency/group\|13\|DDR4\|4000\|0}} {{CAS latency/row\|4000\|0\|19}} \|- {{CAS latency/row\|4000\|0\|18}} \|- {{CAS latency/row\|4000\|0\|17}} \|- {{CAS latency/group\|1\|DDR4\|4133\|1}} Line 342 ⟶ 346: \|- {{CAS latency/row\|4600\|2\|18}} \|- ~~\|-{{Efn\|name="nthword"}}~~ {{CAS latency/group\|1\|DDR4\|4800\|0}} {{CAS latency/row\|4800\|0\|19}}

CAS latency: Difference between revisions