CAS latency: Difference between revisions

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The math didn't add up. Look at the previous sequence of 8 (2**3),2**14,and 1**13
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Removed parameters. | Use this bot. Report bugs. | Suggested by AManWithNoPlan | Category:CS1 maint: ref=harv | via #UCB_Category 1909/2500
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}}</ref> state, with a voltage halfway between high and low. This indeterminate signal is deflected towards high or low by the storage capacitor when a row is made active.
| ref=harv
}}</ref> state, with a voltage halfway between high and low. This indeterminate signal is deflected towards high or low by the storage capacitor when a row is made active.
 
To access memory, a row must first be selected and loaded into the sense amplifiers. This row is then ''active,'' and columns may be accessed for read or write.