CAS latency: Difference between revisions

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Revision as of 19:35, 24 May 2024 edit 83.21.99.202 (talk) →Memory timing examples ← Previous edit		Latest revision as of 12:01, 25 May 2024 edit undo 83.21.99.202 (talk) →Memory timing examples
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Line 128: {{CAS latency/row\|1066\|2\|4}} \|- ! scope="row" rowspan="4041" \| [[DDR3 SDRAM]] {{CAS latency/group\|1\|DDR3\|1066\|2}} {{CAS latency/row\|1066\|2\|7}} \|- {{CAS latency/group\|34\|DDR3\|1333\|1}} {{CAS latency/row\|1333\|1\|9}} \|- {{CAS latency/row\|1333\|1\|8}} \|- {{CAS latency/row\|1333\|1\|7}} Line 310 ⟶ 312: {{CAS latency/row\|3466\|2\|16}} \|- {{CAS latency/group\|12\|DDR4\|3533\|0}} {{CAS latency/row\|3533\|0\|16}} \|-