Overview of deep-sleep and active leakage power in smartphone SoCs.

The design complexity of modern high performance processors calls for innovative design techniques and methodologies for achieving time-to-market goals. New design techniques are also needed to curtail power increases that inherently arise from ever ...

Emerging mobile markets such as wearable electronics and Internet of Things necessitate innovations in embedded non-volatile memory (eNVM) for energy-efficient mobile computing and connectivity. In this paper, we briefly review how conventional eNVM has ...

Planar UTBB FD-SOI technology is an opportunity for energy efficient SOCs in deeply scaled technologies. Thanks to its excellent responsiveness to power management design techniques, this technology brings a significant improvement in terms of ...

In this paper, we discuss some of the most pressing challenges in low-power analog circuit design for sub-28nm technologies. A design methodology suitable for deep submicron low-power analog design is first described. Using the proposed figure of merit, ...

In this paper, emerging low-power interconnect options for CMOS and beyond CMOS technologies are reviewed. First, electrical interconnects based on carbon nanotubes and graphene nanoribbons are discussed. It is found that carbon-based electrical ...

Low power designs demand aggressive power management, which adds complexity and creates both verification and implementation challenges. IEEE Standard 1801 Unified Power Format (UPF) enables early capture of power-intent, early verification of power ...

Low power design techniques and efficient wireless solutions have been critical in enabling mobile computing in a ubiquitous and cost-effective manner. While demand for ubiquitous mobile computing continues to rise thanks to an array of new applications,...

As technology scaling is coming to an end, 3D integration is a promising technology to continue transistor density scaling in the future and facilitate new architectural designs. However heat removal is a serious chalenge in 3D ICs. A promising solution ...

In this paper, we minimize 3D clock power using shutdown gates to selectively turn off unnecessary clock activities. In 3D-IC, shutdown signals require large-sized Through-Silicon-Vias(TSVs), so we propose a simulated annealing(SA) based algorithm along ...

In this paper, we present switched analog circuit (SAC), a new circuit architecture, to implement an energy-efficient mixed-signal dot product (DP) kernel for machine learning and signal processing applications. SAC operates by fast switching the analog ...

The conventional guard band design approach increases the SRAM Wordline (WL) pulse duration to operate successfully in all the process, voltage and temperature (PVT) corners. This can significantly increase the dynamic energy. This work presents a ...

Power management for large last-level caches (LLCs) is important in chip-multiprocessors (CMPs), as the leakage power of LLCs accounts for a significant fraction of the limited on-chip power budget. Since not all workloads need the entire cache, ...

Supercomputers, nowadays, aggregate a large number of nodes sharing the same nominal HW components (eg. processors and GPGPUS). In real-life machines, the chips populating each node are subject to a wide range of variability sources, related to ...

In-situ error-detection and correction techniques have a strong potential to eliminate the worst-case margins in ultra-low-voltage (ULV) pipelines while achieving high variation tolerance. Adding the capability of error detection, however, can incur ...

Supply-noise measurement techniques are becoming increasingly critical in modern digital design, driven by the trend toward smaller, lower-voltage domains. All-digital measurement modules capable of meeting bandwidth and resolution requirements would ...

The recent successful integration of magnetic racetrack memory forecasts a new computing era with unprecedentedly high-density on-chip storage. However, racetrack memory accesses require frequent magnetic domain shifting, introducing overheads in access ...

We propose a power efficient SAD calculator, namely a-SAD. We use MSB-approximation where some highest-order MSB's are approximated to single MSB. Our theoretical analysis shows that this technique simultaneously improves performance and power of SAD ...

In this work, we propose a mixed TFET-MOSFET 8T SRAM cell comprising MOSFET cross-coupled inverters, dedicated TFET read stack and TFET write access transistors. Exploiting both the merits of TFET and MOSFET devices, the proposed SRAM cell provides ...

Software-based path delay fault testing (SPDFT) has been used to identify faulty chips that cannot meet timing constraints due to gross delay defects. In this paper, we propose using SPDFT for a new purpose -- aggressively selecting the operating point ...