NAND flash memory has become an indispensable component in embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cost and high density. Even though NAND flash memory gains popularity as data storage, it ...

Despite recent advances, battery life continues to be a limiting factor in mobile multimedia systems. Significant energy savings can be achieved by adapting systems at run-time to match the execution requirements of different tasks. This paper introduces ...

A requirement-specific decoder design for forward error-correction in 2 Gbps optical fiber communication system ispresented. Low-density parity-check codes are used to achieve high bit error rate performance. Several novel error- decoding architectures are ...

The growing complexity of customizable embedded multi-processor architectures for digital media processing will soon require highly scalable network-on-chip based communication infrastructures. In this paper, we propose xpipes, a scalable and high-...

We present a mixed-mode delay-locked loop (DLL) architecture intended for multiple-phase clock generation. In contrast to analog DLLs, the proposed architecture allows for clock-gating; moreover, circuit simulations indicate that its performance (in terms ...

Modern processors rely heavily on broadcast networks to bypass instruction results to dependent instructions in the pipeline. However, as clock rates increase, architectures get wider, and pipelines get deeper, broadcasting becomes more complex, slower, and ...

Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain modification methodology that transforms the stimuli to be inserted to the ...

In this paper, we present a satisfiability-based algorithm for automatically generating test sequences that target gate-level stuck-at faults in a circuit by using its register-transfer level (RTL)description. Our methodology exploits a popular, unified ...

Due to their simplicity transition faults are often used as targets for test generation to detect delay defects. However, one concern documented in the literature is that of over testing. One of the reasons for overtesting is that DFT approaches, such as ...

The storage for speculative values in superscalar processors is one of the main sources of complexity and power dissipation. In this paper, we present a novel technique to reduce register requirements as well as their dynamic and static power dissipation ...

Power consumption in the register file (RF) forms a considerable fraction of the total power consumption in a chip. With increasing instruction window sizes and issue widths, RF power consumption will suffer a significantly large growth. Using the fact ...

In this paper, we propose a new cell moving algorithm to achieve a desired cell density distribution during the detailed placement stage of a large size standard-cell placement flow. To evaluate our algorithm, we also define a distribution deviation metric ...

Excessive on-chip wire length and fast increasing fabrication cost have been the main factors impairing the effectiveness of monolithic System-on-Chip. This paper investigates a die stacking based system integration strategy (2.5D system integration) to ...

Efficient algorithms for the automatic insertion of flip-flops and buffers are presented. The algorithms have been implemented as part of an automatic repeater insertion tool. The algorithms use a dynamic programming framework to build viable solution ...

The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for high-performancereal-time DSP applications. But the two major weaknesses in VLIW processors prevent the integration of morefunctional units (...

Processor resources required for an effective execution of an application vary across different sections. We propose to take advantage of clustering to turn-off resources that do not contribute to improve performance. First, we present a simple hardware ...

We consider two approaches for reducing the complexity and power dissipation in processors that use separate register file to maintain committed register values. The first approach relies on a distributed implementation of the Reorder Buffer (ROB) that ...