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- research-articleAugust 2024
A 65 nm CMOS Analog Programmable Standard Cell Library for Mixed-Signal Computing
- Pranav O. Mathews,
- Praveen Raj Ayyappan,
- Afolabi Ige,
- Swagat Bhattacharyya,
- Linhao Yang,
- Jennifer O. Hasler
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 10Pages 1830–1840https://doi.org/10.1109/TVLSI.2024.3432916Integrated circuit (IC) design for analog computing requires similar toolflows and synthesis as large-scale digital systems, in-turn necessitating a library of general-purpose analog cells. To this end, we present a programmable, floating-gate (FG)-based ...
- research-articleAugust 2024
The Conjugated Current Mirrors: A General Enhancement in Transconductance Amplifiers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 10Pages 1801–1811https://doi.org/10.1109/TVLSI.2024.3439525This work presents a general enhancement in operational transconductance amplifiers (OTAs) by conjugating the diode-connected topologies of the current mirrors (CMs). The proposed conjugation method provides an internal high-impedance node, by which the ...
- research-articleAugust 2024
M2M: A Fine-Grained Mapping Framework to Accelerate Multiple DNNs on a Multi-Chiplet Architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 10Pages 1864–1877https://doi.org/10.1109/TVLSI.2024.3438549With the advancement of artificial intelligence, the collaboration of multiple deep neural networks (DNNs) has been crucial to existing embedded systems and cloud systems, especially for automatic driving applications as well as augmented and virtual ...
- research-articleAugust 2024
A 20-V Pulse Driver Based on All-nMOS Charge Pump Without Reversion Loss and Overstress in 65-nm Standard CMOS Technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 10Pages 1812–1821https://doi.org/10.1109/TVLSI.2024.3435974This article proposes a high-efficiency all-nMOS bidirectional charge pump (CP) cell and constructs a CP-based high-voltage (HV) pulse driver based on it. Double-diode substrate isolation (DDSI) can extend the maximum supported voltage in a bulk CMOS ...
- research-articleAugust 2024
A High-Precision and High-Dynamic-Range Current-Mode WTA Circuit for Low-Supply-Voltage Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 10Pages 1955–1958https://doi.org/10.1109/TVLSI.2024.3436575This brief proposes a low-voltage, high-precision, and high-dynamic-range current-mode analog winner-take-all (WTA) circuit. The proposed structure employs a new high-gain stage as a feedback network between the input node of each cell and the common node ...
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- research-articleJuly 2024
An Efficient Two-Stage Pipelined Compute-in-Memory Macro for Accelerating Transformer Feed-Forward Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 10Pages 1889–1899https://doi.org/10.1109/TVLSI.2024.3432403Transformer architectures have achieved state-of-the-art performance in various applications. However, deploying transformer models on resource-constrained platforms is still challenging due to its dynamic workloads, intensive computations, and ...
- research-articleJuly 2024
An Electrical-Thermal Co-Simulation Model of Chiplet Heterogeneous Integration Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 10Pages 1769–1781https://doi.org/10.1109/TVLSI.2024.3430498Chiplet heterogeneous integration (CHI) is one of the important technology choices to continue Moore’s law. However, due to the characteristics of high power and low supply voltage in CHI systems, heavy currents need to flow through the power ...
- research-articleJuly 2024
A Low-Cost Quadruple-Node-Upsets Resilient Latch Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 10Pages 1930–1939https://doi.org/10.1109/TVLSI.2024.3430224In this article, a low-cost quadruple-node-upsets resilient latch (LCQRL) design is proposed. To meet the high-reliability demands of safety-critical applications, the latch integrates nine soft-error-interceptive modules (SIMs) to form robust feedback ...
- research-articleJuly 2024
Design of Octave Tuning Range <italic>LC</italic> VCO With Ultralow K<sub>VCO</sub> Using Frequency-Dependent Implicit Capacitance Neutralization Technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 10Pages 1908–1918https://doi.org/10.1109/TVLSI.2024.3430544This article presents a technique of frequency-dependent implicit capacitance neutralization (FD-ICN) among capacitor bank and varactors in LC voltage-controlled oscillator (VCO) to facilitate ultralow VCO gain (<inline-formula> <tex-math notation="LaTeX">...
- research-articleJuly 2024
Novel Optimized Designs of Modulo 2<sup><italic>n</italic></sup>+1 Adder for Quantum Computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 9Pages 1759–1763https://doi.org/10.1109/TVLSI.2024.3418930Quantum modular adders are one of the most fundamental yet versatile quantum computation operations. They help implement the functions of higher complexity, such as subtraction and multiplication, which are used in applications, such as quantum ...
- research-articleJuly 2024
P<sup>2</sup>-ViT: Power-of-Two Post-Training Quantization and Acceleration for Fully Quantized Vision Transformer
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 9Pages 1704–1717https://doi.org/10.1109/TVLSI.2024.3422684Vision transformers (ViTs) have excelled in computer vision (CV) tasks but are memory-consuming and computation-intensive, challenging their deployment on resource-constrained devices. To tackle this limitation, prior works have explored ViT-tailored ...
- research-articleJuly 2024
A Dual-Mode Buck Converter with Light-Load Efficiency Improvement and Seamless Mode Transition Technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 10Pages 1782–1791https://doi.org/10.1109/TVLSI.2024.3422382In order to improve the efficiency over a wide load range, a power converter of the Internet of Things (IoT) usually works in dual modes, which are pulsewidth modulation (PWM) and pulse frequency modulation (PFM). A mixed load detection scheme is adopted ...
- research-articleJuly 2024
An Area-Efficient Systolic Array Redundancy Architecture for Reliable AI Accelerator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 10Pages 1950–1954https://doi.org/10.1109/TVLSI.2024.3421563The increasing demand for data-intensive analytics, driven by the rapid advances in artificial intelligence (AI), has led to the proposal of various AI accelerators. However, as AI-based solutions are being applied to applications that require high ...
- research-articleJuly 2024
A μ-GA Oriented ANN-Driven: Parameter Extraction of 5G CMOS Power Amplifier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 9Pages 1569–1577https://doi.org/10.1109/TVLSI.2024.3414584This article introduces a novel method for extracting crucial parameters from a fifth-generation (5G) CMOS power amplifier (PA) operating at 24 GHz. The proposed method, micro-genetic algorithm artificial neural network (<inline-formula> <tex-math ...
- research-articleJuly 2024
Dynamic Neural Fields Accelerator Design for a Millimeter-Scale Tracking System
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 10Pages 1940–1944https://doi.org/10.1109/TVLSI.2024.3416725This brief introduces a compact-size hardware accelerator for dynamic neural fields (DNF) used in object tracking. To address the substantial computational workload and memory occupancy associated with conventional DNFs, three key approaches are ...
- research-articleJuly 2024
An Adaptive Zero-Current Detector for Single-Inductor Multiple-Output DC-DC Converter With Full-Wave Current Sensor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 9Pages 1764–1768https://doi.org/10.1109/TVLSI.2024.3415475This brief presents an adaptive zero-current detector (ZCD) for the single-inductor multiple-output (SIMO) DC-DC converter with a full-wave current sensor. The innovative adaptive ZCD, which can be applied to the order power distribution control (OPDC) ...
- research-articleJuly 2024
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 10Pages 1919–1929https://doi.org/10.1109/TVLSI.2024.3418961Capitalizing on their versatility and high-performance attributes within heterogeneous designs, increasingly number of field-programmable gate arrays (FPGAs) are integrated into cloud data centers by cloud service providers (CSPs). While CSPs intend to ...
- research-articleJuly 2024
Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 10Pages 1852–1863https://doi.org/10.1109/TVLSI.2024.3418769In recent years, asynchronous circuits have gained attention in neural network chips and Internet of Things (IoT) due to their potential advantages of low power and high performance. However, design efficiency of asynchronous circuits remains low and ...
- research-articleJune 2024
Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads
- Yuan-Chun Luo,
- Anni Lu,
- Janak Sharda,
- Moritz Scherer,
- Jorge Tomas Gomez,
- Syed Shakib Sarwar,
- Ziyun Li,
- Reid Frederick Pinkham,
- Barbara De Salvo,
- Shimeng Yu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 9Pages 1718–1725https://doi.org/10.1109/TVLSI.2024.3415481Heterogeneous 3-D (H3D) integration not only reduces the chip form factor and fabrication cost but also allows the merging of diverse compute paradigms that suit different applications. This is especially attractive when modern algorithms, such as the ...
- research-articleJune 2024
Area Efficient 0.009-mm<sup>2</sup> 28.1-ppm/°C 11.3-MHz ALL-MOS Relaxation Oscillator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 32, Issue 10Pages 1900–1907https://doi.org/10.1109/TVLSI.2024.3416992This article presents an ultrasmall area on-chip relaxation oscillator with low-temperature sensitivity. In this design, a virtual resistor mainly composed of a complementary to absolute temperature (CTAT) voltage reference circuit is implemented to ...