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- ArticleJanuary 2006
A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay Signoff
- K. A. Rajagopal,
- R. Sivakumar,
- N. V. Arvind,
- C. Sreeram,
- Vish Visvanathan,
- Shailendra Dhuri,
- Roopesh Chander,
- Patrick Fortner,
- Subra Sripada,
- Qiuyang Wu
VLSID '06: Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems DesignPages 277–282https://doi.org/10.1109/VLSID.2006.8Leading edge technology advancements have posed big challenges for the digital design flow. Designing multi-million gate ICs at aggressive cycletimes requires new design methodologies and innovative approaches. Hierarchical analysis is a key need to ...
