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- research-articleMarch 2015
Reduced Hardware NOrec: A Safe and Scalable Hybrid Transactional Memory
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 59–71https://doi.org/10.1145/2694344.2694393Because of hardware TM limitations, software fallbacks are the only way to make TM algorithms guarantee progress. Nevertheless, all known software fallbacks to date, from simple locks to sophisticated versions of the NOrec Hybrid TM algorithm, have ...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - research-articleMarch 2015
Asymmetric Memory Fences: Optimizing Both Performance and Implementability
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 531–543https://doi.org/10.1145/2694344.2694388There have been several recent efforts to improve the performance of fences. The most aggressive designs allow post-fence accesses to retire and complete before the fence completes. Unfortunately, such designs present implementation difficulties due to ...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - research-articleMarch 2015
DEUCE: Write-Efficient Encryption for Non-Volatile Memories
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 33–44https://doi.org/10.1145/2694344.2694387Phase Change Memory (PCM) is an emerging Non Volatile Memory (NVM) technology that has the potential to provide scalable high-density memory systems. While the non-volatility of PCM is a desirable property in order to save leakage power, it also has the ...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - research-articleMarch 2015Best Paper
GhostRider: A Hardware-Software System for Memory Trace Oblivious Computation
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 87–101https://doi.org/10.1145/2694344.2694385This paper presents a new, co-designed compiler and architecture called GhostRider for supporting privacy preserving computation in the cloud. GhostRider ensures all programs satisfy a property called memory-trace obliviousness (MTO): Even an adversary ...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - research-articleMarch 2015
Architectural Support for Software-Defined Metadata Processing
- Udit Dhawan,
- Catalin Hritcu,
- Raphael Rubin,
- Nikos Vasilakis,
- Silviu Chiricescu,
- Jonathan M. Smith,
- Thomas F. Knight,
- Benjamin C. Pierce,
- Andre DeHon
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 487–502https://doi.org/10.1145/2694344.2694383Optimized hardware for propagating and checking software-programmable metadata tags can achieve low runtime overhead. We generalize prior work on hardware tagging by considering a generic architecture that supports software-defined policies over ...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - research-articleMarch 2015
Supporting Differentiated Services in Computers via Programmable Architecture for Resourcing-on-Demand (PARD)
- Jiuyue Ma,
- Xiufeng Sui,
- Ninghui Sun,
- Yupeng Li,
- Zihao Yu,
- Bowen Huang,
- Tianni Xu,
- Zhicheng Yao,
- Yun Chen,
- Haibin Wang,
- Lixin Zhang,
- Yungang Bao
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 131–143https://doi.org/10.1145/2694344.2694382This paper presents PARD, a programmable architecture for resourcing-on-demand that provides a new programming interface to convey an application's high-level information like quality-of-service requirements to the hardware. PARD enables new ...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - research-articleMarch 2015
CoolAir: Temperature- and Variation-Aware Management for Free-Cooled Datacenters
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 253–265https://doi.org/10.1145/2694344.2694378Despite its benefits, free cooling may expose servers to high absolute temperatures, wide temperature variations, and high humidity when datacenters are sited at certain locations. Prior research (in non-free-cooled datacenters) has shown that high ...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - research-articleMarch 2015
More is Less, Less is More: Molecular-Scale Photonic NoC Power Topologies
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 283–296https://doi.org/10.1145/2694344.2694377Molecular-scale Network-on-Chip (mNoC) crossbars use quantum dot LEDs as an on-chip light source, and chromophores to provide optical signal filtering for receivers. An mNoC reduces power consumption or enables scaling to larger crossbars for a reduced ...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - invited-talkMarch 2015
Architectural Support for Cyber-Physical Systems
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPage 1https://doi.org/10.1145/2694344.2694375Cyber-physical systems are integrations of computation, communication networks, and physical dynamics. Although time plays a central role in the physical world, all widely used software abstractions lack temporal semantics. The notion of correct ...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - research-articleMarch 2015
Temporally Bounding TSO for Fence-Free Asymmetric Synchronization
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 45–58https://doi.org/10.1145/2694344.2694374This paper introduces a temporally bounded total store ordering (TBTSO) memory model, and shows that it enables nonblocking fence-free solutions to asymmetric synchronization problems, such as those arising in memory reclamation and biased locking.
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - research-articleMarch 2015
Beyond the PDP-11: Architectural Support for a Memory-Safe C Abstract Machine
- David Chisnall,
- Colin Rothwell,
- Robert N.M. Watson,
- Jonathan Woodruff,
- Munraj Vadera,
- Simon W. Moore,
- Michael Roe,
- Brooks Davis,
- Peter G. Neumann
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 117–130https://doi.org/10.1145/2694344.2694367We propose a new memory-safe interpretation of the C abstract machine that provides stronger protection to benefit security and debugging. Despite ambiguities in the specification intended to provide implementation flexibility, contemporary ...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - research-articleMarch 2015
SPECS: A Lightweight Runtime Mechanism for Protecting Software from Security-Critical Processor Bugs
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 517–529https://doi.org/10.1145/2694344.2694366Processor implementation errata remain a problem, and worse, a subset of these bugs are security-critical. We classified 7 years of errata from recent commercial processors to understand the magnitude and severity of this problem, and found that of 301 ...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - research-articleMarch 2015
DeNovoSync: Efficient Support for Arbitrary Synchronization without Writer-Initiated Invalidations
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 545–559https://doi.org/10.1145/2694344.2694356Current shared-memory hardware is complex and inefficient. Prior work on the DeNovo coherence protocol showed that disciplined shared-memory programming models can enable more complexity-, performance-, and energy-efficient hardware than the state-of-...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - research-articleMarch 2015
CommGuard: Mitigating Communication Errors in Error-Prone Parallel Execution
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 311–323https://doi.org/10.1145/2694344.2694354As semiconductor technology scales towards ever-smaller transistor sizes, hardware fault rates are increasing. Since important application classes (e.g., multimedia, streaming workloads) are data-error-tolerant, recent research has proposed techniques ...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - research-articleMarch 2015
ApproxHadoop: Bringing Approximations to MapReduce Frameworks
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 383–397https://doi.org/10.1145/2694344.2694351We propose and evaluate a framework for creating and running approximation-enabled MapReduce programs. Specifically, we propose approximation mechanisms that fit naturally into the MapReduce paradigm, including input data sampling, task dropping, and ...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - research-articleMarch 2015
Synchronization Using Remote-Scope Promotion
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 73–86https://doi.org/10.1145/2694344.2694350Heterogeneous system architecture (HSA) and OpenCL define scoped synchronization to facilitate low overhead communication across a subset of threads. Scoped synchronization works well for static sharing patterns, where consumer threads are known a ...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - research-articleMarch 2015
Improving Agility and Elasticity in Bare-metal Clouds
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 145–159https://doi.org/10.1145/2694344.2694349Bare-metal clouds are an emerging infrastructure-as-a-service (IaaS) that leases physical machines (bare-metal instances) rather than virtual machines, allowing resource-intensive applications to have exclusive access to physical hardware. Unfortunately,...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1 - research-articleMarch 2015
Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers
- Johann Hauswald,
- Michael A. Laurenzano,
- Yunqi Zhang,
- Cheng Li,
- Austin Rovinski,
- Arjun Khurana,
- Ronald G. Dreslinski,
- Trevor Mudge,
- Vinicius Petrucci,
- Lingjia Tang,
- Jason Mars
ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 223–238https://doi.org/10.1145/2694344.2694347As user demand scales for intelligent personal assistants (IPAs) such as Apple's Siri, Google's Google Now, and Microsoft's Cortana, we are approaching the computational limits of current datacenter architectures. It is an open question how future ...
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ACM SIGPLAN Notices: Volume 50 Issue 4ACM SIGARCH Computer Architecture News: Volume 43 Issue 1