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- ArticleMay 2002
Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model
CODES '02: Proceedings of the tenth international symposium on Hardware/software codesignPages 199–204https://doi.org/10.1145/774789.774830We present a method of runtime configuration scheduling in reconfigurable SoC design. As a model of computation in system representation, we use a popular formal model of computation, hierarchical FSM (HFSM) with synchronous dataflow (SDF) model, in ...
- ArticleMay 2002
Fast system-level power profiling for battery-efficient system design
CODES '02: Proceedings of the tenth international symposium on Hardware/software codesignPages 157–162https://doi.org/10.1145/774789.774822An increasing disparity between the energy requirements of portable electronic devices and available buttry capacities is driving the development of new design methodologies for battery-efficient systems. A crucial requirement for battery efficient ...
- ArticleMay 2002
A study of CodePack: optimizing embedded code space
CODES '02: Proceedings of the tenth international symposium on Hardware/software codesignPages 103–108https://doi.org/10.1145/774789.774811CodePack is a code compression system used by IBM in its PowerPC family of embedded processors. CodePack combines high compression capability along with fast and simple decoding hardware. IBM did not release much information about the design of the ...
- ArticleMay 2002
Multi-objective design space exploration using genetic algorithms
CODES '02: Proceedings of the tenth international symposium on Hardware/software codesignPages 67–72https://doi.org/10.1145/774789.774804In this work, we provide a technique for efficiently exploring a parameterized system-on-a-chip (SoC) architecture to find all Pareto-optimal configurations in a multi-objective design space. Globally, our approach uses a parameter dependency model of ...
- ArticleMay 2002
Worst-case performance analysis of parallel, communicating software processes
CODES '02: Proceedings of the tenth international symposium on Hardware/software codesignPages 37–42https://doi.org/10.1145/774789.774798In this paper we present a method to perform static timing analysis of SystemC models, that describe parallel, communicating software processes. The paper combines a worst-case execution time (WCET) analysis with an analysis of the communication ...
