Simple and powerful modeling of concurrency and reactivityalong with their efficient implementation in the simulationkernel are crucial to the overall usefulness of systemlevel models using the C++-based modeling frame-works.However, the concurrency ...

In this paper, we investigate the benefits of a flexible,application-specific instruction set by adding a run-timeReconfigurable Functional Unit (RFU) to a VLIWprocessor. Preliminary results on the motion estimationstage in an MPEG4 video encoder are ...

We consider the implication of deep sub-micron VLSItechnology on the design of communication frameworksfor parallel DSP systems-on-chip. We assert thatdistributed data transfer and control mechanisms arenecessary to manage many independent ...

We present the formal verification of the floating-point multiplier in the Intel IA-32 Pentium® microprocessor. The verification is based on a combination of theorem-proving and BDD based model-checking tasks performed in a unified hardware verification ...

This paper introduces an extension to the RMS schedulingtechnique that we call "Hot Swapping". Hot Swappingenables a system to choose between various selectedimplementations of one task on-the-fly and thus to optimizethe system's cost (e.g. power ...

To enable fast and accurate evaluation of HW/SW implementationchoices of on-chip communication, we presenta method to automatically generate timed OS simulationmodels. The method generates the OS simulation modelswith the simulation environment as a ...

This paper focuses on I-cache behaviourenhancement through the application of high-levelcode transformations. Specifically, a flow for theiterative application of the I-Cache performanceoptimizing transformations is proposed. Theprocedure of applying ...

Complex embedded systems consist of hardware and softwarecomponents from different domains, such as control and signalprocessing, many of them supplied by different IP vendors. Theembedded system designer faces the challenge to integrate, optimizeand ...