Export Citations
Save this search
Please login to be able to save your searches and receive alerts for new content matching your search criteria.
- research-articleJanuary 2019
A stable routing algorithm for mobile ad hoc network using fuzzy logic system
International Journal of Advanced Intelligence Paradigms (IJAIP), Volume 14, Issue 3-4Pages 248–259https://doi.org/10.1504/ijaip.2019.103412The mobile ad hoc network (MANET) is an infrastructure-less network, where the nodes communicate either directly or indirectly through intermediate nodes. The network topology can change frequently due to its dynamic nature and limited resource ...
- research-articleOctober 2017
Formal and simulation-based timing analysis of industrial-ethernet sercos III over TSN
Time-Sensitive Networking (TSN) is becoming more important in automotive and industrial sectors. There is no clear strategy how to use TSN to improve and migrate the established real-time protocols without excluding legacy devices. This paper presents a ...
- short-paperSeptember 2016
Using IVML to model the topology of big data processing pipelines
SPLC '16: Proceedings of the 20th International Systems and Software Product Line ConferencePages 204–208https://doi.org/10.1145/2934466.2934476Creating product lines of Big Data stream processing applications introduces a number of novel challenges to variability modeling. In this paper, we discuss these challenges and demonstrate how advanced variability modeling capabilities can be used to ...
- research-articleJune 2014
Reconfigurable network testbed for evaluation of datacenter topologies
DIDC '14: Proceedings of the sixth international workshop on Data intensive distributed computingPages 11–20https://doi.org/10.1145/2608020.2608023Software-defined networking combined with distributed and parallel applications has the potential to deliver optimized application performance at runtime. In order to investigate this enhancement and design future implementation, a datacenter with a ...
- research-articleMarch 2014
Exploiting Emergence in On-Chip Interconnects
IEEE Transactions on Computers (ITCO), Volume 63, Issue 3Pages 570–582https://doi.org/10.1109/TC.2012.273To solve the grand challenges in contemporary chip design, such as process-to-core mapping, energy reduction, and maintenance of programmer/hardware abstraction, we advocate for self-optimizing (emergent) networks-on-chip (NoC). In these networks, ...
- research-articleAugust 2013
On the role of topology in autonomously coping with failures in content dissemination systems
CAC '13: Proceedings of the 2013 ACM Cloud and Autonomic Computing ConferenceArticle No.: 14, Pages 1–10https://doi.org/10.1145/2494621.2494635Content dissemination systems comprise a large number of nodes that organize themselves into different topologies. In this paper, we explore the role of topologies in autonomously coping with failures. The topologies we consider are based on regular, ...
- ArticleJuly 2012
Soft rough sets and topologies
ICIC'12: Proceedings of the 8th international conference on Intelligent Computing Theories and ApplicationsPages 103–110https://doi.org/10.1007/978-3-642-31576-3_14In this paper, we consider a new kind of soft sets. Based on them, we propose soft rough approximations and give their properties. Soft rough sets are defined and their topological structures are obtained. Moreover, we investigate the relationship ...
- research-articleMay 2011
Multi-objective topology synthesis and FPGA prototyping framework of application specific network-on-chip
GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSIPages 55–60https://doi.org/10.1145/1973009.1973021Network-on-Chip (NoC) topology synthesis problem targets to generate NoC topology for multiple system design objectives such as performance and area. A multi-objective NoC synthesis and prototyping framework based on FPGA platform is proposed to design ...
- ArticleApril 2011
Experiments on islands
The use of segmented populations (Islands) has proven to be advantageous for Genetic Programming (GP). This paper discusses the application of segmentation and migration strategies to a system for Linear Genetic Programming (LGP). Besides revisiting ...
- ArticleJuly 2010
Parallel kinematics for haptic feedback in three degrees of freedom: application in a handheld laparoscopic telemanipulation system
In this paper parallel kinematic structures are analyzed to realize a haptic joystick with three translational degrees of freedom. The Chebychev-Grübler-Kutzbach criterion is applied to determine kinematic topologies. Resulting topologies are listed ...
- ArticleJuly 2010
Parallel Kinematics for Haptic Feedback in Three Degrees of Freedom: Application in a Handheld Laparoscopic Telemanipulation System
Proceedings, Part I, of the International Conference on Haptics: Generating and Perceiving Tangible Sensations - Volume 6191Pages 219–224https://doi.org/10.1007/978-3-642-14064-8_32In this paper parallel kinematic structures are analyzed to realize a haptic joystick with three translational degrees of freedom. The Chebychev---Grübler---Kutzbach criterion is applied to determine kinematic topologies. Resulting topologies are listed ...
- research-articleFebruary 2010
Predicting the performance of application-specific NoCs implemented on FPGAs
FPGA '10: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arraysPages 23–32https://doi.org/10.1145/1723112.1723118Modern FPGAs are able to implement complex systems such as Systems-on-Chips (SoCs) and Networks-on-Chips (NoCs). Appropriate NoC topology choices for ASICs have been investigated and typically topologies that can be easily mapped to a two-dimensional ...
- research-articleOctober 2007
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 15, Issue 10Pages 1081–1090https://doi.org/10.1109/TVLSI.2007.893649Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3-D NoC are compared to that of 2-D NoC. Physical constraints, such as the maximum number of planes that can be ...
- research-articleApril 2004
WebNews agent
RIAO '04: Coupling approaches, coupling media and coupling languages for information retrievalPage 932WebNews Intelligent Agent is a new agent from the Competitive Intelligence Platform "DIGIMIND EVOLUTION" dedicated to aggregating and monitoring news and events from one's own web sources. Based on advanced mathematical algorithms from the field of ...
- articleApril 2003
Weighted finite automata and metrics in cantor space
We show how weighted finite automata define topologies on the set of all ω-words over a finite alphabet X. Moreover, we give a characterization of these topologies in terms of topologies on Xω induced by languages U ⊆ X*.
- research-articleAugust 2001
The Reflection Map with Discontinuities
Mathematics of Operations Research (MOOR), Volume 26, Issue 3Pages 447–484https://doi.org/10.1287/moor.26.3.447.10588We study the multidimensional reflection map on the spaces D([0, T], ℝk) and D([0, ∞), ℝk) of right-continuous ℝk-valued functions on [0, T] or [0, ∞) with left limits, endowed with variants of the Skorohod (1956) M1 topology. The reflection map was used ...
- ArticleNovember 2000
Systematic testing of protocol robustness: case studies on mobile IP and MARS
Systematic testing of robustness by evaluation of synthesized scenarios STRESS is a methodology developed for the systematic testing of protocols, and includes algorithms for generating topologies and event sequences that rigorously test the correctness ...
- ArticleNovember 1990
Topologies for the parallel backtracking Prolog engine
MICRO 23: Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecturePages 237–242Some multicomputer networks for the implementation of the PBPE, a Parallel Backtracking Prolog Engine designed at the University of Bari, Italy, are considered. Two main subsystems, one for the management of clauses and another for interpretation of ...